EDBT 2026 Demo / reviewers in the wild / expert
Mary N. Youssef
dblp:66/2013
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 1985
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.0 | 1 | 1985 | Timing influenced layout design · DAC 1985 |
Electronic design automation › physical design › placement and routing
timing-driven placement and routing |
0.0 | 1 | 1985 | Timing influenced layout design · DAC 1985 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1985 | Timing influenced layout designabstractWe present a new approach to the automatic layout design for VLSI chips which incorporates timing information to influence the placement and wiring processes. This approach is an extension of the hierarchical layout method, in which placement and wiring are performed simultaneously [1]. We add a third phase of timing to the hierarchy, without affecting the computational complexity of the basic algorithm. Michael Burstein, Mary N. Youssef |
DAC | 2 |