We propose to adapt an earlier unconditionally secure communication system for ground vehicular network to Unmanned Air Systems (UASs). First, one recommended change is to adopt IEEE 802.16d for long range wireless communications (up to 75 km) for drone to drone communications. Second, we propose to strengthen the security of UAS communications by incorporating unconditionally secure key exchanges between certification authorities (CA), which are air traffic control (ATC) centers, and ground communication centers (also can be called road side devices (RSDs)). The proposed key exchange scheme is known as the Kirchhoff Law Johnson Noise (KLJN) scheme, which is unconditionally secure. The KLJN provides equivalent or better security but with much lower cost as compared to the quantum key distribution (QKD). The exchanged keys will be used to create digital signatures for messages between UASs. Third, the digital signatures combined with certificates issued for each UAS by CAs will be used for authentication of messages, which will further improve the security between UASs.

Large integer multiplication is a major performance bottleneck in fully homomorphic encryption (FHE) schemes over the integers. In this paper two optimised multiplier architectures for large integer multiplication are proposed. The first of these is a low-latency hardware architecture of an integer-FFT multiplier. Secondly, the use of low Hamming weight (LHW) parameters is applied to create a novel hardware architecture for large integer multiplication in integer-based FHE schemes. The proposed architectures are implemented, verified and compared on the Xilinx Virtex-7 FPGA platform. Finally, the proposed implementations are employed to evaluate the large multiplication in the encryption step of FHE over the integers. The analysis shows a speed improvement factor of up to 26.2 for the low-latency design compared to the corresponding original integer-based FHE software implementation. When the proposed LHW architecture is combined with the low-latency integer-FFT accelerator to evaluate a single FHE encryption operation, the performance results show that a speed improvement by a factor of approximately 130 is possible.

Cryptographic hash functions can be used to provide strong security and privacy for Radio Frequency Identification (RFID) systems. In this paper, two application-oriented optimized SHA-256 hardware designs for low-cost RFID are presented. These are implemented on UMC 0.13 µm CMOS standard cell technology. One of the proposed designs achieves the smallest area (8,394 gates) while the other achieves the lowest power consumption (2.86 µW) in comparison to previous SHA-256 designs and SHA-3 finalist candidates reported in the literature to date. Furthermore, if the designs are used in low-cost RFID applications in which the input being authenticated is less than 400 bits, the two designs can be further optimized to utilise just 6,125 gates and consume 2.3 µW of power.

In recent years, numerous authentication protocols for radio frequency identification (RFID) systems have been proposed to protect privacy. Due to the hardware resource limitation on RFID tags, the majority of these protocols are based on symmetric-key ciphers. However, most of them lack scalability at the reader side as they require a linear or logarithmic search proportional to the number of tags in the system in order to authenticate a tag. Recently proposed scalable protocols require a constant-time search and utilize hash look-up tables. However, the storage requirement of the hash-table in these protocols is very large, therefore not practical. Moreover, previous proposals do not support dynamic resizing where the number of tags changes during the life time of the RFID system. In this paper, a new Re-Hash technique is presented to reduce the hash-table storage in constant-time authentication protocols. To the best of our knowledge, it offers the smallest storage cost in comparison to previous proposals. The Re-Hash technique is also further adapted to support the dynamic scalability for RFID systems.

This paper presents a parallel framework of grid-based numerical algorithms where data dependencies between grid zones can be modeled by a directed acyclic graph (DAG). It consists of three parts on how to partition, order and calculate the vertices of digraph. Numerical results using hundreds of processors on two parallel machines show the efficiencies and moderate scalability of this framework