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Sanjay Vishin

dblp:66/2241 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 4

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Energy-efficient computing · 81% Processor architecture and microarchitecture · 19%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Energy-efficient computing › power management › system-level power management
hierarchical power management
0.212013
Hierarchical power management for asymmetric multi-core in dark silicon era · DAC 2013
Energy-efficient computing
power management
0.212013
Hierarchical power management for asymmetric multi-core in dark silicon era · DAC 2013
Processor architecture and microarchitecture › multicore design › heterogeneous multicore
asymmetric multicore
0.012013
Hierarchical power management for asymmetric multi-core in dark silicon era · DAC 2013
Processor architecture and microarchitecture
multicore design
0.012013
Hierarchical power management for asymmetric multi-core in dark silicon era · DAC 2013
Energy-efficient computing
thermal design power
0.012013
Hierarchical power management for asymmetric multi-core in dark silicon era · DAC 2013
Energy-efficient computing
thermal management
0.012013
Hierarchical power management for asymmetric multi-core in dark silicon era · DAC 2013

Methods — techniques the papers use, named apart from their topics

control theory · 0.2
YearPublicationVenuePosition
2013 Power-performance modeling on asymmetric multi-cores
abstract
Asymmetric multi-core architectures have recently emerged as a promising alternative in a power and thermal constrained environment. They typically integrate cores with different power and performance characteristics, which makes mapping of workloads to appropriate cores a challenging task. Limited number of performance counters and heterogeneous memory hierarchy increase the difficulty in predicting the performance and power consumption across cores in commercial asymmetric multi-core architectures. In this work, we propose a software-based modeling technique that can estimate performance and power consumption of workloads for different core types. We evaluate the accuracy of our technique on ARM big. LITTLE asymmetric multi-core platform.
Mihai Pricopi, Thannirmalai Somu Muthukaruppan, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin
CASES5
2013 Hierarchical power management for asymmetric multi-core in dark silicon era
abstract
Asymmetric multi-core architectures integrating cores with diverse power-performance characteristics is emerging as a promising alternative in the dark silicon era where only a fraction of the cores on chip can be powered on due to thermal limits. We introduce a hierarchical power management framework for asymmetric multi-cores that builds on control theory and coordinates multiple controllers in a synergistic manner to achieve optimal power-performance efficiency while respecting the thermal design power budget. We integrate our framework within Linux and implement/evaluate it on real ARM big.LITTLE asymmetric multi-core platform.
Thannirmalai Somu Muthukaruppan, Mihai Pricopi, Vanchinathan Venkataramani, Tulika Mitra, Sanjay Vishin
DAC5
1995 Exploiting Parallelism in Cache Coherency Protocol Engines
Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, Michael Parkin, Bill Radke, Sanjay Vishin
Euro-Par7
1995 The S3.mp Scalable Shared Memory Multiprocessor
Andreas Nowatzyk, Gunes Aybay, Michael C. Browne, Edmund J. Kelly, Michael Parkin, Bill Radke, Sanjay Vishin
ICPP (1)7