The use of multi-view images acquired by a 360-degree camera can reconstruct a 3D space with a wide area. There are 3D reconstruction methods from equirectangular images based on NeRF and 3DGS, as well as Novel View Synthesis (NVS) methods. On the other hand, it is necessary to overcome the large distortion caused by the projection model of a 360-degree camera when equirectangular images are used. In 3DGS-based methods, the large distortion of the 360-degree camera model generates extremely large 3D Gaussians, resulting in poor rendering accuracy. We propose ErpGS, which is Omnidirectional GS based on 3DGS to realize NVS addressing the problems. ErpGS introduce some rendering accuracy improvement techniques: geometric regularization, scale regularization, and distortion-aware weights and a mask to suppress the effects of obstacles in equirectangular images. Through experiments on public datasets, we demonstrate that ErpGS can render novel view images more accurately than conventional methods.

Semantic segmentation is a fundamental task in medical image analysis and autonomous driving and has a problem with the high cost of annotating the labels required in training. To address this problem, semantic segmentation methods based on semi-supervised learning with a small number of labeled data have been proposed. For example, one approach is to train a semantic segmentation model using images with annotated labels and pseudo labels. In this approach, the accuracy of the semantic segmentation model depends on the quality of the pseudo labels, and the quality of the pseudo labels depends on the performance of the model to be trained and the amount of data with annotated labels. In this paper, we generate pseudo labels using zero-shot annotation with the Segment Anything Model (SAM) and Contrastive Language-Image Pretraining (CLIP), improve the accuracy of the pseudo labels using the Unified Dual-Stream Perturbations Approach (UniMatch), and use them as enhanced labels to train a semantic segmentation model. The effectiveness of the proposed method is demonstrated through the experiments using the public datasets: PASCAL and MS COCO.

Gaussian Splatting (GS) has gained attention as a fast and effective method for novel view synthesis. It has also been applied to 3D reconstruction using multi-view images and can achieve fast and accurate 3D reconstruction. However, GS assumes that the input contains a large number of multi-view images, and therefore, the reconstruction accuracy significantly decreases when only a limited number of input images are available. One of the main reasons is the insufficient number of 3D points in the sparse point cloud obtained through Structure from Motion (SfM), which results in a poor initialization for optimizing the Gaussian primitives. We propose a new 3D reconstruction method, called Sparse2DGS, to enhance 2DGS in reconstructing objects using only three images. Sparse2DGS employs DUSt3R, a fundamental model for stereo images, along with COLMAP MVS to generate highly accurate and dense 3D point clouds, which are then used to initialize 2D Gaussians. Through experiments on the DTU dataset, we show that Sparse2DGS can accurately reconstruct the 3D shapes of objects using just three images.

In this paper, we propose a method to refine depth maps estimated by Multi-View Stereo (MVS) with Neural Radiance Field (NeRF) optimization to estimate depth maps from multi-view images with high accuracy. MVS estimates the depths on object surfaces with high accuracy, and NeRF estimates the depths at object boundaries with high accuracy. The key ideas of the proposed method are (i) to combine MVS and NeRF to utilize the advantages of both in depth map estimation, (ii) not to require any training process, therefore no training dataset and ground truth are required, and (iii) to use NeRF for depth map refinement. Through a set of experiments using the Redwood-3dscan dataset, we demonstrate the effectiveness of the proposed method compared to conventional depth map estimation methods.

In this paper, we propose a method to improve the accuracy of depth map estimation from multi-view images using Neural Radiance Fields (NeRF). A depth map can be estimated from multi-view images using Multi-View Stereo (MVS), which can estimates the depths inside objects with high accuracy, while NeRF can estimate the depths at object boundaries with high accuracy. We consider using both advantages to improve the accuracy of depth map estimation from multi-view images and making NeRF as a refinement module. Through a set of experiments using a public MVS dataset, we demonstrate the effectiveness of the proposed method compared to conventional depth map estimation methods.

Abstract PatchMatch Stereo is a method for generating a depth map from stereo images by repeating spatial propagation and view propagation. The concept of PatchMatch Stereo can be easily extended to Multi-View Stereo (MVS). In this paper, we present PatchMatch Multi-View Stereo (PM-MVS), which is a highly accurate 3D reconstruction method that can be used in various environments. Three techniques are introduced to PM-MVS: (i) matching score evaluation, (ii) viewpoint selection, and (iii) outlier filtering. The combination of normalized cross-correlation with bilateral weights and geometric consistency between viewpoints is used to improve the estimation accuracy of depth and normal maps at object boundaries and poor-texture regions. For each pixel, viewpoints used for stereo matching are carefully selected in order to improve robustness against disturbances such as occlusion, noise, blur, and distortion. Outliers are removed from reconstructed 3D point clouds by a weighted median filter and consistency-based filters assuming multi-view geometry. Through a set of experiments using public multi-view image datasets, we demonstrate that the proposed method exhibits efficient performance compared with conventional methods.

In this paper, we improve the performance of CNN-based fingerprint recognition without increasing the size of CNN, while training CNN on a limited number of data in public databases to guarantee reproducibility. We propose a Texture-Minutiae Network (TMNet) for extracting texture and minutia features based on ResNet-34. We introduce multiple attention mechanisms to TMNet in order to improve performance on fingerprint recognition without increasing the size of the network. Through experiments of performance evaluation using FVC2004 DB1, DB2, and DB3, we demonstrate that the proposed method is more effective than the conventional methods for fingerprint recognition.

In this paper, we propose a robust and accurate image correspondence method by combining SuperPoint + SuperGlue (SP+SG) and Local feature matching with TRansformers (LoFTR). The proposed method finds corresponding points on regions with rich texture by SP+SG and those with poor texture by LoFTR since SP+SG exhibits high localization accuracy of image correspondence and LoFTR exhibits high robustness against poor texture regions. The proposed method can be used for image correspondence in SfM to not only improve the estimation accuracy of camera parameters in SfM, but also to improve the reconstruction accuracy and expand the reconstruction area in MVS. Through experiments on the ETH3D dataset, we demonstrate that the proposed method achieves more accurate 3D reconstruction than conventional methods, and also show the impact of image correspondence accuracy in SfM on multi-view 3D reconstruction.

Remote sensing using Synthetic Aperture Radar (SAR) is an indispensable technology for effective disaster management, owing to its large observation area, cloud penetrating ability and its independence from sunlight, which allow for quick observation of large disaster affected areas disregarding weather or time of the day. In particular, 3D measurement from SAR images could contribute a better understanding of the affected area and speed up decision making. Most methods require prior knowledge of the scene such as ground control points to achieve a reasonable level of 3D measurement accuracy, resulting in losing the advantage of quick observation. In this paper, we propose an accurate 3D measurement method from SAR images based on the principle of stereo vision without any prior knowledge of the scene. We demonstrate the effectiveness of our method compared with the conventional method through a set of experiments using an airborne SAR image dataset.

Although most fingerprint matching methods utilize minutia points and/or texture of fingerprint images as fingerprint features, the frequency spectrum is also a useful feature since a fingerprint is composed of ridge patterns with its inherent frequency band. We propose a novel CNN-based method for extracting fingerprint features from texture, minutiae, and frequency spectrum. In order to extract effective texture features from local regions around the minutiae, the minutia attention module is introduced to the proposed method. We also propose new data augmentation methods, which takes into account the characteristics of fingerprint images to increase the number of images during training since we use only a public dataset in training, which includes a few fingerprint classes. Through a set of experiments using FVC2004 DB1 and DB2, we demonstrated that the proposed method exhibits the efficient performance on fingerprint verification compared with a commercial fingerprint matching software and the conventional method.

Synthetic Aperture Radar (SAR) has been used to acquire images for analyzing geometrical properties of the ground surface. In this paper, we propose a method of detecting seismic ground deformation from the airborne SAR images with parameter optimization. The optimal parameters in ground deformation detection are estimated so as to minimize the reprojection error in the radar projection model based on the idea of bundle adjustment. We demonstrate the effectiveness of our method in detecting seismic ground deformation through the experiment using the airborne SAR images taken before and after the Kumamoto Earthquake in 2016.

BACKGROUND: The combination of systematic evolution of ligands by exponential enrichment (SELEX) and deep sequencing is termed high-throughput (HT)-SELEX, which enables searching aptamer candidates from a massive amount of oligonucleotide sequences. A clustering method is an important procedure to identify sequence groups including aptamer candidates for evaluation with experimental analysis. In general, aptamer includes a specific target binding region, which is necessary for binding to the target molecules. The length of the target binding region varies depending on the target molecules and/or binding styles. Currently available clustering methods for HT-SELEX only estimate clusters based on the similarity of full-length sequences or limited length of motifs as target binding regions. Hence, a clustering method considering the target binding region with different lengths is required. Moreover, to handle such huge data and to save sequencing cost, a clustering method with fast calculation from a single round of HT-SELEX data, not multiple rounds, is also preferred. RESULTS: We developed fast string-based clustering (FSBC) for HT-SELEX data. FSBC was designed to estimate clusters by searching various lengths of over-represented strings as target binding regions. FSBC was also designed for fast calculation with search space reduction from a single round, typically the final round, of HT-SELEX data considering imbalanced nucleobases of the aptamer selection process. The calculation time and clustering accuracy of FSBC were compared with those of four conventional clustering methods, FASTAptamer, AptaCluster, APTANI, and AptaTRACE, using HT-SELEX data (>15 million oligonucleotide sequences). FSBC, AptaCluster, and AptaTRACE could complete the clustering for all sequence data, and FSBC and AptaTRACE performed higher clustering accuracy. FSBC showed the highest clustering accuracy and had the second fastest calculation speed among all methods compared. CONCLUSION: FSBC is applicable to a large HT-SELEX dataset, which can facilitate the accurate identification of groups including aptamer candidates. AVAILABILITY OF DATA AND MATERIALS: FSBC is available at http://www.aoki.ecei.tohoku.ac.jp/fsbc/.

A clustering method for high-throughput sequencing with SELEX pools (HT-SELEX) is crucial for selecting different types of aptamer candidates. The fast and accurate clustering method is indispensable for an enormous sequence data produced by HT-SELSEX. We have already developed a fast motif-based clustering (FMBC) method for HT-SELEX data implemented by R language. FMBC exhibited high accuracy of sequence clustering compared with conventional methods, while the processing time of FMBC is longer than AptaCluster. This paper proposes the parallel implementation of FMBC using Python with multi-threading to improve the performance of FMBC. Experimental evaluation using the NCBI SRA data of SRR3279661 from BioProject PRJNA315881 demonstrated that parallel FMBC exhibited higher accuracy of clustering and shorter processing time than conventional methods.

Observation of seismic ground deformation is one of the fundamental topics in remote sensing. A Synthetic Aperture Radar (SAR) has been used to obtain images representing geometrical properties of the ground surface. SAR images can be taken in nearly all weather conditions and in nearly all time. This paper proposes a ground deformation observation method using image correspondence matching, which employs phase-only correlation to estimate displacement between two SAR intensity images with sub-pixel accuracy. Through experiments using airborne SAR intensity images of the Kumamoto Earthquake, we demonstrate that the proposed method exhibits the efficient performance in observing seismic ground deformation.

This paper proposes an outlier and artifact removal method for multiview stereo. The proposed method introduces the three filters, which check (i) consistency among depth maps and their visibility, (ii) left-right consistency and (iii) consistency between the depth map and color intensity, respectively. The proposed method removes outliers and artifacts from depth maps generated by PatchMatch Multi-View Stereo. We demonstrate that the proposed method exhibits the efficient performance on 3D reconstruction compared with conventional methods through a set of experiments using public datasets and under practical situations.

Elevation measurement using Synthetic Aperture Radar (SAR) is one of fundamental techniques in remote sensing. Interferometric SAR (InSAR), which is the most popular technique of elevation measurement using SAR, uses the phase differences between the signals received by SAR antennas. InSAR requires Ground Control Points (GCPs) to measure absolute elevation values, although GCPs cannot be obtained in emergency situations. In addition, rapid observation, i.e., on-board processing, is expected in emergency situations. Addressing the above problem, this paper proposes an elevation measurement method using interferometry and radargrametry from single-pass airborne SAR images. Through the experiments, we demonstrate that the proposed method exhibits efficient performance in elevation measurement.

In this study, we propose a formal design system for tamper-resistant cryptographic hardwares based on Generalized Masking Scheme (GMS). The masking scheme, which is a state-of-the-art masking-based countermeasure against higher-order differential power analyses (DPAs), can securely construct any kind of Galois-field (GF) arithmetic circuits at the register transfer level (RTL) description, while most other ones require specific physical design. In this study, we first present a formal design methodology of GMS-based GF arithmetic circuits based on a hierarchical dataflow graph, called GF arithmetic circuit graph (GF-ACG), and present a formal verification method for both functionality and security property based on Gröbner basis. In addition, we propose an automatic generation system for GMS-based GF multipliers, which can synthesize a fifth-order 256-bit multiplier (whose input bit-length is 256 × 77) within 15 min.

Elevation measurement using Synthetic Aperture Radar (SAR) is one of fundamental techniques in remote sensing. The cross-track Interferometric SAR (InSAR), which is the most popular technique of elevation measurement using SAR, uses the phase differences between the signals received by SAR antennas. Single-pass InSAR can be achieved by a single platform with two antennas. InSAR requires Ground Control Points (GCPs) to measure absolute elevation values, although it is a time-consuming and cost-intensive task to acquire GCPs. Addressing the above problem, this paper proposes an elevation measurement method using two SAR intensity images taken by a single-pass airborne SAR system. A projection model is derived to apply the principle of stereo vision to elevation measurement from SAR images. Phase-Only Correlation is employed to obtain accurate correspondence between two SAR images having below 1-pixel disparities. Through the experiment using SAR images, we demonstrate that the proposed method exhibits efficient performance in elevation measurement.

This paper presents an efficient approach to verifying higher-degree Galois-field (GF) arithmetic circuits. The proposed method describes GF arithmetic circuits using a mathematical graph-based representation and verifies them by a combination of algebraic transformations and a new verification method based on natural deduction for first-order predicate logic with equal sign. The natural deduction method can verify one type of higher-degree GF arithmetic circuit efficiently while the existing methods require an enormous amount of time, if they can verify them at all. In this paper, we first apply the proposed method to the design and verification of various Reed-Solomon (RS) code decoders. We confirm that the proposed method can verify RS decoders with higher-degree functions while the existing method needs a lot of time or fail. In particular, we show that the proposed method can be applied to practical decoders with 8-bit symbols, which are performed with up to 2,040-bit operands. We then demonstrate the design and verification of the Advanced Encryption Standard (AES) encryption and decryption processors. As a result, the proposed method successfully verifies the AES decryption datapath while an existing method fails.

A lot of feature-based correspondence matching methods have been proposed in the field of computer vision, image processing and pattern recognition. These methods are also effective for biometric recognition. In general, in the case of feature-based matching methods, the matching score is calculated as a ratio between the number of feature points and corresponding points. These methods need to normalize image deformation by fitting an image transformation model to images according to the correspondence between images. Then, the matching score is calculated from the normalized images so as to take into consideration image deformation. On the other hand, this paper proposes a score calculation method which calculates a matching score from positional information of corresponding point pairs. The proposed method does not need any deformation model defined for each biometric trait to handle image deformation. The combination of the matching scores defined by the number of corresponding points and the positional information improves the performance of biometric recognition algorithms, since these scores play a complementary role in decision. Through a set of experiments using a palmprint image database, we demonstrate that the proposed method exhibits efficient performance for biometric recognition.

Combination of a supply-current equalizer (EQ) and a micro EM probe sensor (EMS) exhibits strong resiliency against major three DPA/DEMA/LEMA low-cost side-channel attacks on a cryptographic processor. Test-chip measurements with 128bit AES cryptographic processor in 0.18μm CMOS successfully demonstrate the secret key protection from all three attacks. A digital-oriented circuit implementation together with a careful design optimization minimize the hardware overhead of EQ and EMS to +33%, +1.6% in area, +7.6%, +0.15% in power, and ~0%, -0.2% in performance of an unprotected AES, respectively.

A side-channel attack exploiting EM-field leakage from a cryptographic processor IC is an existing serious threat to our information society. EM radiation during the IC operation is captured by an EM probe and the correlation to the crypto processing is statistically analyzed to reveal the secret information although it is protected in a software (algorithm) domain. This paper presents a reactive hardware (implementation) domain countermeasure against this EM attack, namely EM attack sensor. An on-chip sensor coil detects EM probe approach and reacts to protect the secret information from the tamper attack. The sensor concept and low-cost digital circuit implementation are reviewed, and the detail of the design-automation methodology highly-compatible to standard EDA tools is presented. A small hardware overhead of the sensor is silicon-proven in an actual 0.18μm CMOS test-chip implementation together with a 128bit AES crypto core. The test-chip measurements demonstrate successful sensor operation against the actual EM probe attack.

Elevation measurement using Synthetic Aperture Radar (SAR) is one of crucial applications in remote sensing, since the use of SAR in elevation measurement makes it possible to measure a wide range of planar area and not to set any monitoring device on the ground. Most of conventional methods need Ground Control Points (GCPs) to achieve accurate 3D measurement, where GCP acquisition is a time-consuming and cost-intensive task. Addressing the above problem, this paper proposes a novel stereo radargrammetry method using airborne SAR images without GCP. We define a new sensor model with only parameters provided in SAR image acquisition which derives from the principle of stereo vision. We employ bundle adjustment so as to minimize reprojection errors in 3D measurement, since the proposed sensor model is based on stereo vision. We also employ Phase-Only Correlation (POC), which is a sub-pixel image matching method using phase information obtained by Discrete Fourier Transform (DFT) of given images, to obtain dense and accurate correspondence between two SAR images. Through an experiment using SAR images, we demonstrate that the proposed method exhibits efficient performance of radargrammetry compared with Interferommetric SAR (InSAR).

This paper proposes a sequential online 3D reconstruction system using dense stereo matching for a non-expert user, which can sequentially reconstruct accurate and dense 3D point clouds when the new image is captured. The proposed system is based on a novel processing pipeline of sequential online 3D reconstruction with two key techniques: (i) camera parameter estimation of Structure from Motion (SfM) and (ii) dense stereo correspondence matching using Phase-Only Correlation (POC). The user can confirm the reconstruction result and add supplementary images to the system in order to reconstruct a complete 3D model as needed. Through a set of experiments, the proposed system exhibits efficient performance in terms of reconstruction accuracy and computation time compared with the conventional system.

In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault analysis (DFA), such as redundancy calculation, masked and-or, and wave dynamic differential logic. The proposed countermeasure can thwart both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept that removes the dependency between FSs and secret data. The postmanufacture configuration of the CDBs allows minimization of the overhead in operating frequency that comes from manufacture variability. In this paper, we also present an implementation of the proposed countermeasure in application-specified integrated circuit, and describe its configuration method. We then investigate the hardware overhead of the proposed countermeasure for an advanced encryption standard processor and demonstrate its validity through an experiment.

The use of tablet PCs is spreading rapidly, and accordingly users browsing and inputting personal information in public spaces can often be seen by third parties. Unlike conventional mobile phones and notebook PCs equipped with distinct input devices (e.g., keyboards), tablet PCs have touchscreen keyboards for data input. Such integration of display and input device increases the potential for harm when the display is captured by malicious attackers. This paper presents the description of reconstructing tablet PC displays via measurement of electromagnetic (EM) emanation. In conventional studies, such EM display capture has been achieved by using non-portable setups. Those studies also assumed that a large amount of time was available in advance of capture to obtain the electrical parameters of the target display. In contrast, this paper demonstrates that such EM display capture is feasible in real time by a setup that fits in an attaché case. The screen image reconstruction is achieved by performing a prior course profiling and a complemental signal processing instead of the conventional fine parameter tuning. Such complemental processing can eliminate the differences of leakage parameters among individuals and therefore correct the distortions of images. The attack distance, 2 m, makes this method a practical threat to general tablet PCs in public places. This paper discusses possible attack scenarios based on the setup described above. In addition, we describe a mechanism of EM emanation from tablet PCs and a countermeasure against such EM display capture.

This paper presents a multi-finger knuckle recognition system and proposes a finger knuckle region extraction algorithm from a video sequence. The use of video sequences makes it possible to achieve stable and robust finger knuckle region extraction, since the optimal image frame can be selected from a set of image frames to extract a region to be matched for each finger. Through a set of experiments, we demonstrate that the extraction rates of the proposed algorithm are 96.4%, 99.4%, 97.6% and 96.4% for index, middle, ring and little fingers, respectively, which are acceptable in practice. The result indicates that four fingers can be used for person authentication in most cases. We also demonstrate that the use of multiple finger knuckle regions exhibits efficient performance for person authentication.

This paper presents a formal method for designing cryptographic processor datapaths on the basis of arithmetic circuits over Galois fields (GFs). The proposed method describes GF arithmetic circuits in the form of hierarchical graph structures, where nodes represent sub-circuits whose functions are defined by arithmetic formulae over GFs, and edges represent data dependency between nodes. In this paper, we first introduce the application of graph representation to arithmetic circuits over extension fields of${\mbi {GF}}({{\mbi {p}}^{\mbi {m}}})$$({\mbi {p}} \geq {\bf 2})$and composite fields, which are commonly used in the design of cryptographic processors. The newly proposed graph representation can be formally verified through symbolic computation techniques based on polynomial reduction and Gröbner basis. We then demonstrate the capabilities of the proposed approach through an experimental design of a 128-bit AES (Advanced Encryption Standard) datapath including multiplicative inversion circuits over the composite field${\mbi {GF}}{(((2^2)^2)^2})$. The results show that the proposed method can describe such practical datapaths, as well as that complete verification of such a datapath can be carried out within a short period of time.

This paper proposes a 3D reconstruction algorithm for urban environments from video sequences taken by an in-vehicle fisheye camera. The proposed algorithm employs (i) fisheye camera calibration to apply the general Structure from Motion to video sequences taken by the fisheye camera and (ii) accurate, dense and robust feature point tracking using phase-based correspondence matching. Experimental evaluation using the video sequence taken by the in-vehicle fisheye camera demonstrates that the proposed algorithm exhibits efficient performance of 3D reconstruction compared with the laser measurement system.

In this paper, we present an efficient countermeasure against Fault Sensitivity Analysis (FSA) based on a configurable delay blocks (CDBs). FSA is a new type of fault attack which exploits the relationship between fault sensitivity and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against Differential Fault Analysis (DFA) such as redundancy calculation, Masked AND-OR and Wave Dynamic Differential Logic (WDDL). The proposed countermeasure can detect both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li's countermeasure concept which removes the dependency between fault sensitivities and secret data. Post-manufacture configuration of the delay blocks allows minimization of the overhead in operating frequency which comes from manufacture variability. In this paper, we present an implementation of the proposed countermeasure, and describe its configuration method. We also investigate the hardware overhead of the proposed countermeasure implemented in ASIC for an AES module and demonstrate its validity through an experiment using a prototype FPGA implementation.

Reconstructing occluded regions of the object is to automatically detect the occluded regions and background in the image and reconstruct these regions using image interpolation. This paper proposes a novel occluded region reconstruction method using Fast Weighted Principal Component Analysis (FW-PCA). The computation time of the weighted PCA can be reduced by using only the effective regions when calculating the principal component scores. The occluded regions are accurately detected by recursively updating the weight for each pixel in the image using FW-PCA. Then, the occluded regions can be reconstructed using the final weight. Thorough a set of experiments, we demonstrate that the proposed method exhibits higher performance than the conventional method.

This paper proposes an accurate, dense and robust wide-baseline stereo correspondence matching method combining ASIFT (Affine-SIFT) and POC (Phase-Only Correlation). ASIFT-based matching is robust against perspective deformation of the stereo images, while the corresponding points are sparse. POC-based matching can find dense correspondence, while the corresponding points are not reliable in the case of the wide-baseline stereo. The complementary use of ASIFT and POC makes it possible to find accurate and dense stereo correspondence regardless of the length of camera baseline. Through a set of experiments, we demonstrate that the proposed method exhibits efficient performance compared with the conventional methods. We also apply the proposed method to 3D reconstruction from multi-view images.

This paper proposes a Graphics Processing Unit (GPU) implementation of the stereo correspondence matching using Phase-Only Correlation (POC). The use of high-accuracy stereo correspondence matching based on POC makes it possible to measure accurate 3D shape of the object using stereo vision, while the drawback of POC-based approach is its high computational cost. Addressing this problem, we propose a GPU implementation of POC-based correspondence matching. Through a set of experiments using a variety of GPUs, we demonstrate that the proposed implementation is high-speed and high-efficiency compared with the CPU implementation. We also apply the proposed approach to a real-time 3D measurement system.

This paper proposes a formal approach to designing Galois-field (GF) arithmetic circuits, which are widely used in modern cryptographic processors. Our method describes GF arithmetic circuits in a hierarchical manner with high-level directed graphs associated with specific GFs and arithmetic functions. The proposed circuit description can be effectively verified by symbolic computations based on polynomial reduction using Grobner bases. The verified description is then translated into the equivalent hardware description language (HDL) codes, which are available for the conventional design flow. We first describe the proposed graph representation and present an example of the description and verification. The significant advantage of the proposed approach is demonstrated through experimental designs of parallel multipliers over GF(2m) for different word lengths and irreducible polynomials. The result shows that the proposed approach has a definite capability of formally verifying practical GF arithmetic circuits for which the conventional techniques fail. We also propose an application of this approach to cryptographic processor design. The target considered here is a 128-bit advanced encryption standard (AES) data path with a loop architecture. To the best of the authors' knowledge, this is the first verification of this type of practical AES data path. We present a detailed description of the AES data path and its verification. The proposed approach successfully verifies the AES data path description within 800 s.

The first contribution of our paper is that we propose a platform, a design strategy, and evaluation criteria for a fair and consistent hardware evaluation of the second-round SHA-3 candidates. Using a SASEBO-GII field-programmable gate array (FPGA) board as a common platform, combined with well defined hardware and software interfaces, we compare all 256-bit version candidates with respect to area, throughput, latency, power, and energy consumption. Our approach defines a standard testing harness for SHA-3 candidates, including the interface specification for the SHA-3 module on our testing platform. The second contribution is that we provide both FPGA and 90-nm CMOS application-specific integrated circuit (ASIC) synthesis results and thereby are able to compare the results. Our third contribution is that we release the source code of all the candidates and by using a common, fixed, publicly available platform, our claimed results become reproducible and open for a public verification.

This paper proposes a 2D face recognition algorithm using phase-based correspondence matching. The phase information obtained from 2D DFT (Discrete Fourier Transform) of images contains important information of image representation. The phase-based image matching is successfully applied to sub-pixel image registration tasks for computer vision applications and image recognition tasks for biometric authentication applications. Hierarchical block matching using phase information, i.e, phase-based correspondence matching, can find the corresponding points on the input image from the reference points on the registered image with sub-pixel accuracy. For face recognition, the phase-based correspondence matching is useful for minute change of texture, such as facial expression change, illumination change, etc. Experimental evaluation using the CSU Face Identification Evaluation System with the FERET database demonstrates efficient recognition performance of the proposed algorithm compared with the conventional face recognition algorithms.

Image inpainting is a technique for estimating missing pixel values in an image by using the pixel value information obtained from neighbor pixels of a missing pixel or the prior knowledge derived from learning the object class. In this paper, we propose a fast and accurate image inpainting method using similarity of the subspace. The proposed method generates the subspace from many images related to the object class in the learning step and estimates the missing pixel values of the input image belonging to the same object class so as to maximize the similarity between the input image and the subspace in the inpainting step. Through a set of experiments, we demonstrate that the proposed method exhibits excellent performance in terms of both inpainting accuracy and computation time compared with conventional algorithms.

This paper presents an improved design for a Level-Crossing ADC (LCADC) that incorporates both an equivalent- time method and a clocked comparator. The LCADC is experimentally validated using a 65 nm clocked comparator.

This paper introduces a new Level-Crossing ADC (LCADC) architecture which employs the novel use of a clocked comparator. The proposed LCADC can measure a timing noise spectrum with wide dynamic range and wide frequency range. An extension of the underlying theory of the performance measurement of an LCADC is also included.

This paper presents a systematic design approach to provide the optimized Rivest-Shamir-Adleman (RSA) processors based on high-radix Montgomery multipliers satisfying various user requirements, such as circuit area, operating time, and resistance against side-channel attacks. In order to involve the tradeoff between the performance and the resistance, we apply four types of exponentiation algorithms: two variants of the binary method with/without Chinese Remainder Theorem (CRT). We also introduces three multiplier-based datapath-architectures using different intermediate data forms: 1) single form, 2) semi carry-save form, and 3) carry-save form, and combined them with a wide variety of arithmetic components. Their radices are parameterized from 28to 2128. A total of 242 datapaths for 1024-bit RSA processors were obtained for each radix. The potential of the proposed approach is demonstrated through an experimental synthesis of all possible processors with a 90-nm CMOS standard cell library. As a result, the smallest design of 861 gates with 118.47 ms/RSA to the fastest design of 0.67 ms/RSA at 153\thinspace 862 gates were obtained. In addition, the use of the CRT technique reduced the RSA operation time of the fastest design to 0.24 ms. Even if we employed the exponentiation algorithm resistant to typical side-channel attacks, the fastest design can perform the RSA operation in less than 1.0 ms.

This paper proposes a high-accuracy image correction method using SIFT (Scale-Invariant Feature Transform) and POC (Phase-Only Correlation) for multi-projector display. The accurate correspondence between the projector and camera images is required to achieve seamless imagery in a multiprojector display. The conventional methods need to project and take special light patterns on a screen many times to obtain the correspondence. On the other hand, the proposed method needs to take only one snapshot of ordinary images so as to realize real-time geometric correction of projector images. Through a set of experiments, we demonstrate that the proposed method is effective for practical use of multi-projector display compared with the conventional methods.

This paper proposes a multi-stage scale estimation algorithm using phase-based correspondence matching for electron microscope images. Consider a sequence of microscope images of the same target object, where the image magnification is gradually increased so that the final image has a very large scale factor S (e.g., S=1,000) with respect to the initial image. The problem considered in this paper is to estimate the overall scale factor S of the given image sequence. The proposed scale estimation technique provides a new methodology for high-accuracy magnification calibration of electron microscopes. Experimental evaluation using Mandelbrot images as precisely scale-controlled image sequence shows that the proposed method can estimate the scale factor S=1,000 with approximately 0.1%-scale error. This paper also describes an application of the proposed algorithm to the magnification calibration of an actual STEM (Scanning Transmission Electron Microscope).

When a cellular phone is lost or stolen, it may be used improperly or the personal information may be stolen from it by a malicious user. Biometric authentication such as palm-print recognition is the strongest of the personal authentication technologies designed to prevent such misuse. Ito et al. proposed several palmprint recognition schemes using correspondence matching based on the phase-only correlation among various schemes. However, these schemes require a palmprint image to be captured with the hand touching the dedicated device, while palmprint images must be captured without such physical contact when using cellular phones. Thus these schemes cannot be applied to cellular phones since there are large positioning gaps and large differences in brightness and distortion between the images. Furthermore, they are not implemented in the cellular phone and their performances are not evaluated either.

This paper proposes new chosen-message power-analysis attacks for public-key cryptosystems based on modular exponentiation, where specific input pairs are used to generate collisions between squaring operations at different locations in the two power traces. Unlike previous attacks of this kind, the new attack can be applied to all standard implementations of the exponentiation process, namely binary (left-to-right and right-to-left), m-ary, and sliding window methods. The proposed attack can also circumvent typical countermeasures, such as the Montgomery powering ladder and the double-add algorithm. The effectiveness of the attack is demonstrated in experiments with hardware and software implementations of RSA on an FPGA and a PowerPC processor, respectively. In addition to the new collision generation methods, a highly accurate waveform matching technique is introduced for detecting the collisions even when the recorded signals are noisy and there is a certain amount of clock jitter.

This paper proposes a novel method for aligning two signals using the information contained in the overlapped band. In particular the proposed method aligns two signals by compensating both time-delay and phase-offset in the second signal using the estimated gradient of phase difference in the overlapped band. Compared with other conventional methods, this method can align two signals without requiring a pilot tone or additional hardware. The proposed method was experimentally validated using RF pulses.

This paper presents a palmprint recognition algorithm using principal component analysis (PCA) of phase information in 2D (two-dimensional) discrete Fourier transforms (DFTs) of palmprint images. To achieve highly robust palmprint recognition, the proposed algorithm (i) limits the frequency bandwidth, and (ii) averages phase spectra using multiple palmprint images captured from the same hand at an enrollment stage. Through a set of experiments, we demonstrate that the proposed method can significantly reduce computational cost without sacrificing recognition performance compared with our previous work using phase-only correlation (POC) - an image matching technique using the phase components in 2D DFTs of given images. Also, the resulting performance is much higher than those of conventional palmprint recognition algorithms which apply PCA to palmprint images, or phase spectra directly.

Palmprint images taken from a camera are distorted due to movement of a hand and fingers. To achieve reliable palmprint recognition, it is necessary to employ a recognition algorithm dealing with nonlinear distortion, while the conventional algorithms only consider the rigid body transformation between palmprint images. This paper proposes a palmprint recognition algorithm using phase-based correspondence matching. In order to handle nonlinear distortion, the proposed algorithm (i) finds corresponding points between two images using phase-based correspondence matching and (ii) evaluates a similarity between local image blocks around the corresponding points. Experimental evaluation using a palmprint image database demonstrates efficient recognition performance of the proposed algorithm compared with conventional algorithms.

High-accuracy image registration is an important fundamental task in many fields, such as image sensing, image/video processing, computer vision, etc. In order to evaluate accuracy of image registration algorithms, the reference images transformed with known parameters have to be used. Reference images taken by a camera may include human errors, while reference images generated by a computer may require pixel interpolation in the process. To address these problems, this paper proposes a performance evaluation method using the Mandelbrot set which is one of the famous fractals. Experimental evaluation shows effectiveness of the proposed method.

Simple power analysis attacks with chosen-message techniques were applied to an RSA processor implemented with standard CMOS technology on ASIC, and the different characteristics of power waveforms caused by two types of implementation (ASIC and FPGA) were investigated in detail. We also applied comparative power analysis an advanced power analysis attack in which a pair of input data was used to enhance the waveform pattern for modular exponentiation. The power dissipation of modular squaring in the difference waveform was greatly reduced when compared to modular multiplication, allowing all of the secret key bits to be successfully revealed.

Sometimes, mirrors provide illusions that distort physical laws. In these methods, the illusions become "real" as your visual, tactile, and auditory senses are immersed in the world inside the mirror. Our methods allows you to experience a mirror illusion through three modalities of feedback (visual, haptic, and auditory) and perceive a boundary less transition between the real world and the world inside the mirror. This approach is expected to open new possibilities for using mirrors in the fields of media art or virtual reality.

Abstract Various forms of art and entertainment involve many different characters, and advances in human interfaces have necessitated physical interactions in order to develop an improved sense of reality. In this paper we propose a method for generating the motions of characters using multidimensional keyframe animation in parallel with real‐time physical simulation. The method generates characters capable of physical interaction, and also allows animators to use traditional methods for designing character motion. We have implemented the system and confirmed its effectiveness experimentally.

Various high-performance hardware architectures for Galois counter mode (GCM) in conjunction with various advanced encryption standard (AES) circuits and multiplier-adders are proposed. A total of 17 GCM-AES circuits were synthesized by using a 130-nm CMOS standard cell library, and the trade-offs between speed and hardware resources were evaluated. Our flexible architectures achieved a wide variety of performances from compact (2.56 Gbps with 34.5 Kgates) to high speed (62.6 Gbps with 979.3 Kgates). All of our architectures support key sizes of 128, 192, and 256 bits, while only one previous approach does. Even with variable-length key support, our architecture also achieved the highest hardware efficiency (defined as throughput per gate) among the designs using the same generation of process technology.

This paper presents SPA (Simple Power Analysis) attacks against public-key cryptosystems implemented on an FPGA platform. The SPA attack investigates a power waveform generated by a cryptographic module, and reveals a secret key in the module. We focus on chosen-message SPA attacks, which enhances the differences of operating waveforms between multiplication and squaring correlated to the secret key by using the input of particular messages. In particular, Yen showed a unique SPA attack against RSA cryptosystem, but no verification experiment using actual software or hardware was performed. In this paper, we implemented four-types of RSA processors on an FPGA platform in combination with two variants of the Montgomery multiplication algorithm and two different types of multipliers for SPA attacks experiments. Then we demonstrated effectiveness of various chosen-message attacks as well as Yen’s method, and investigated the characteristics of the attacks depending on the hardware architectures.

The present paper proposes a systematic design approach to provide the optimal high-radix Montgomery multipliers for an RSA processor satisfying user requirements. We introduces three multiplier-based architectures using different intermediate-data forms ((i) single form, (ii) semi carry-save form, and (iii) carry-save form), and combined them with a wide variety of arithmetic components. Their radices are also parameterized from 28to 264. A total of 202 designs for 1,024-bit RSA processors were obtained for each radix, and were synthesized using a 90-nm CMOS standard cell library. The smallest design of 0.9 Kgates with 137.8 ms/RSA to the fastest design of 1.8 ms/RSA at 74.7 Kgates were then obtained. In addition, the optimal design to meet the user requirements can be easily obtained from all the combinations. In addition to choosing the datapath architecture, the arithmetic component, and the radix parameters, the proposed systematic approach can also adopt other process technologies.

This paper proposes a three-dimensional (3D) body scanning system that uses passive stereo vision with a robot arm. So far, the reported 3D body scanning systems employ active 3D measurement methods. However, active methods use structured illumination or laser scanning, which is not desirable in many systems applied to human. A major problem of using passive stereo vision for 3D measurement is its low accuracy. In addition, multiple stereo images captured from different viewpoints are necessary to cover the whole body at an appropriate distance. Addressing these problems, we have newly developed an eye-in-hand system based on passive stereo vision, where a phase-based image matching technique is employed for sub-pixel disparity estimation. Through a set of experiments, we demonstrate that the proposed system can capture 3D shape of human body with high quality.

This paper proposes a practical palmprint recognition algorithm using two-dimensional (2D) phase information. The proposed algorithm (i) reduces the registered data size by registering quantized phase information and (ii) deals with nonlinear distortion between palmprint images by local block matching. Experimental evaluation using palmprint image databases clearly demonstrates efficient recognition performance of the proposed algorithm compared with the conventional palmprint recognition algorithms.

This paper proposes an efficient dental radiograph registration algorithm using Phase-Only Correlation (POC). The use of phase components in 2D (two-dimensional) discrete Fourier transforms of dental radiograph images makes it possible to achieve highly robust image registration and recognition. The proposed algorithm finds correspondence points between two images using the sub-pixel correspondence search using POC and corrects nonlinear distortion based on the Thin-Plate Spline (TPS) model. Experimental evaluation using a dental radiograph database indicates that the proposed algorithm exhibits efficient recognition performance even for distorted radiographs.

An integrated and effective metal artifact reduction method named Metal Erasing (ME) especially suited to dental applications is proposed. Layout of metals is identified as metal-only tomogram, using its characteristics of X-ray opacity and simple image processing technique of binarization together with backward projection. Metal-only sinogram is calculated by forward projection of the metal-only tomogram, and identifies corrupted areas on the original sinogram. The areas are then replaced by interpolation, and filtered back projection (FBP) produces a tomogram without figures of metals. The metals can be reproduced by overlaying already obtained metal-only tomogram utilizing linear characteristics of FBP. It is expected that the ME method can be incorporated into commercial CT scanners easily with reasonable computational overhead.

SPA (Simple Power Analysis) attacks against RSA cryptosystems are enhanced by using chosen-message scenarios. One of the most powerful chosen-message SPA attacks was proposed by Yen et. al. in 2005, which can be applied to various algorithms and architectures, and can defeat the most popular SPA countermeasure using dummy multiplication. Special input values of −1 and a pair of −X and X can be used to identify squaring operations performed depending on key bit stream. However, no experimental result on actual implementation was reported. In this paper, we implemented some RSA processors on an FPGA platform and demonstrated that Yen’s attack with a signal filtering technique clearly reveal the secret key information in the actual power waveforms.

In the present paper, we introduce high-performance hardware architectures for the 128-bit block cipher CLEFIA and evaluate their ASIC performances in comparison with the ISO/IEC 18033-3 standard block ciphers (AES, Camellia, SEED, CAST-128, MISTY1, and TDEA). We designed five types of hardware architectures for CLEFIA, combining two loop structures and three F-functions. These designs were synthesized with a 90-nm CMOS standard cell library, and size and speed performances were evaluated. The highest hardware efficiency (defined as throughput/gates) obtained was 400.96 Kbps/gates, which is 1.5 times higher than previously achieved efficiencies.

This paper presents an arithmetic module generator based on an arithmetic description language called ARITH. The use of ARITH makes it possible to describe a wide variety of arithmetic algorithms in a unified manner. The ARITH descriptions are formally verified in the generator even if the arithmetic algorithms include unconventional number systems for operands or internal variables. The proposed generator also optimizes arithmetic algorithms by using performance profiles derived from the previous generation. From these features, we can obtain high-performance arithmetic modules whose functions are completely verified at the algorithm level. In this paper, we demonstrate that the optimal prefix adders improved the performance of generated arithmetic modules such as multipliers in comparison with the standard prefix adders.

This paper presents an efficient algorithm for iris recognition using phase-based image matching--an image matching technique using phase components in 2D Discrete Fourier Transforms (DFTs) of given images. Experimental evaluation using CASIA iris image databases (versions 1.0 and 2.0) and Iris Challenge Evaluation (ICE) 2005 database clearly demonstrates that the use of phase components of iris images makes possible to achieve highly accurate iris recognition with a simple matching algorithm. This paper also discusses major implementation issues of our algorithm. In order to reduce the size of iris data and to prevent the visibility of iris images, we introduce the idea of 2D Fourier Phase Code (FPC) for representing iris information. The 2D FPC is particularly useful for implementing compact iris recognition devices using state-of-the-art Digital Signal Processing (DSP) technology.

This paper introduces a systematic approach to designing high-performance parallel adders based on Counter Tree Diagrams (CTDs). By using CTDs, we can describe addition algorithms at various levels of abstraction. A high-level CTD represents a network of coarse-grained components associated with word-level operands, whereas a low-level CTD represents a network of primitive components that can be directly mapped onto physical devices. The level of abstraction in circuit representation can be changed by decomposition of CTDs. We can derive possible variations of adder structures by decomposing a high-level CTD into low-level CTDs in a formal manner. In this paper, we focus on an application of CTDs to the design of redundant arithmetic adders with limited carry propagation. For any redundant number representation, we can obtain the optimal adder structure by trying every possible CTD decomposition and CTD-variable encoding. The potential of the proposed approach is demonstrated through an experimental synthesis of Redundant-Binary (RB) adders with CMOS standard cell libraries. We can successfully obtain RB adders that achieve an about 30-40% improvement in terms of power-delay product compared with conventional designs.

This paper presents a formal approach to verify arithmetic circuits using symbolic computer algebra. Our method describes arithmetic circuits directly with high-level mathematical objects based on weighted number systems and arithmetic formulae. Such circuit description can be effectively verified by polynomial reduction techniques using Grobner Bases. In this paper, we describe how the symbolic computer algebra can be used to describe and verify arithmetic circuits. The advantageous effects of the proposed approach are demonstrated through experimental verification of some arithmetic circuits such as multiply-accumulator and FIR filter. The result shows that the proposed approach has a definite possibility of verifying practical arithmetic circuits where the conventional techniques failed.

Dental radiographs have been used for the accurate assessment and treatment of dental diseases. For an accurate diagnosis, the complete geometric registration between radiographs is required. The perspective projection between two radiographs may be observed, even if they are taken from the same oral regions of the subject. This paper presents an efficient dental radiograph registration algorithm using Phase-Only Correlation (POC) function. The use of phase components in 2D (two-dimensional) discrete Fourier transforms of dental radiograph images makes possible to achieve highly robust image registration and recognition. Experimental evaluation using a dental radiograph database indicates that the proposed algorithm exhibits efficient recognition performance even for distorted radiographs.

This paper presents a technique for high-accuracy correspondence search between two rectified images using 1D phase-only correlation (POC). The correspondence search between stereo images can be reduced to 1D search through image rectification. However, we usually employ block matching with 2D rectangular image blocks for finding the best matching point in the 1D search. We propose the use of 1D POC (instead of 2D block matching) for stereo correspondence search. The use of 1D POC makes possible significant reduction in computational cost without sacrificing reconstruction accuracy compared with the 2D POC-based approach. Also, the resulting reconstruction accuracy is much higher than those of conventional stereo matching techniques using SAD (sum of absolute differences) and SSD (sum of squared differences) combined with sub-pixel disparity estimation.

Simple power analysis (SPA) was applied to an RSA processor with a high-radix Montgomery multiplier on an FPGA platform, and the different characteristics of power waveforms caused by two types of multiplier (built-in and custom) were investigated in detail. The authors also applied an active attack where input data was set to a specific pattern to control the modular multiplication. The power dissipation for the multiplication was greatly reduced in comparison with modular squaring, resulting in success in revealing all of the secret key bits

We propose differential power analysis (DPA) with a phase-based waveform matching technique. Conventionally, a trigger signal and a system clock are used to capture the waveform traces, but the signals always contain jitter-related deviations, and this degrades the accuracy of the statistical analysis. Our method can adjust for this timing deviation with a higher resolution than the sampling rate by post-processing on the measured waveforms. Therefore, no modification of the measuring equipment is required. Our method can also defeat DPA countermeasures creating distorted waveforms with random delays or dummy cycles. We implemented Data Encryption Standard (DES) software with and without the countermeasure on a Z80 microprocessor, and demonstrated the advantages of our method in comparison with a conventional attack.

The authors propose a compact hardware architecture for the 64-bit block cipher CAST-128, which is one of the ISO/IEC 18033-3 standard algorithms. Part of the complexity of CAST-128 is its use of various S-boxes in various sequences, and three types of f-function are switched depending on the round numbers. Therefore a large amount of hardware resources are required for a straight-forward implementation. In order to create compact CAST-128 hardware, the authors minimized the number of S-box components, and merged the three f-functions into one arithmetic component. The CAST-128 hardware based on the proposed architecture was synthesized using 0.13μm and 0.18-μm CMOS standard cell libraries and small, practical circuits of 26.4-39.5 Kgates and 189.9-614.7 Mbps were obtained.

A major approach for palmprint recognition today is to extract feature vectors corresponding to individual palmprint images and to perform palmprint matching based on some distance metrics. One of the difficult problems in feature-based recognition is that the matching performance is significantly influenced by many parameters in feature extraction process, which may vary depending on environmental factors of image acquisition. This paper presents a palmprint recognition algorithm using phase-based image matching. The use of phase components in 2D (two-dimensional) discrete Fourier transforms of palmprint images makes possible to achieve highly robust palmprint recognition. Experimental evaluation using a palmprint image database clearly demonstrates an efficient matching performance of the proposed algorithm.

This paper presents an implementation of iris recognition algorithm using phase-based image matching-an image matching technique using phase components in 2D discrete Fourier transforms (DFTs) of given images. Our experimental observation clearly shows that the use of phase components of iris images makes possible to achieve highly accurate iris recognition even for low-quality iris images. In this paper, we consider the problem of designing a compact phase-based iris recognition algorithm especially suitable for hardware implementation. We also present prototype implementation of an iris recognition system based on the proposed algorithm. The prototype system fully utilizes state-of-the-art DSP (digital signal processor) technology to achieve real-time iris recognition capability within a compact hardware module.

A major approach for fingerprint recognition today is to extract minutiae from fingerprint images and to perform fingerprint matching based on the number of corresponding minutiae pairings. One of the most difficult problems in fingerprint recognition has been that the recognition performance is significantly influenced by fingertip surface condition, which may vary depending on environmental or personal causes. Addressing this problem, this paper presents a fingerprint recognition algorithm using phase-based image matching. The use of phase components in 2D (two-dimensional) discrete Fourier transforms of fingerprint images makes possible to achieve highly robust fingerprint recognition for low-quality fingerprints. Experimental evaluation using a set of fingerprint images captured from fingertips with difficult conditions (e.g., dry fingertips, rough fingertips, allergic-skin fingertips) demonstrates an efficient recognition performance of the proposed algorithm compared with a typical minutiae-based algorithm.

A major approach for iris recognition today is to generate feature vectors corresponding to individual iris images and to perform iris matching based on some distance metrics. One of the difficult problems in feature-based iris recognition is that the matching performance is significantly influenced by many parameters in feature extraction process, which may vary depending on environmental factors of image acquisition. This paper presents an efficient algorithm for iris recognition using phase-based image matching. The use of phase components in 2D (two-dimensional) discrete Fourier transforms of iris images makes possible to achieve highly robust iris recognition in a unified fashion with a simple matching algorithm. Experimental evaluation using an iris image database clearly demonstrates an efficient matching performance of the proposed algorithm.

This paper proposes a face recognition system that uses (i) passive stereo vision to capture three-dimensional (3D) facial information and (ii) 3D matching using a simple ICP (iterative closest point) algorithm. So far, the reported 3D face recognition techniques assume the use of active 3D measurement for 3D facial capture. However, active methods employ structured illumination (structure projection, phase shift, gray-code demodulation, etc.) or laser scanning, which is not desirable in many human recognition applications. A major problem of using passive stereo vision for 3D measurement is its low accuracy, and thus no passive methods for 3D face recognition have been reported previously. Addressing this problem, we have newly developed a high-accuracy 3D measurement system based on passive stereo vision, where phase-based image matching is employed for sub-pixel disparity estimation. This paper presents the first attempt to create a practical face recognition system based on fully passive 3D reconstruction.

This paper presents a generic objected-oriented framework of evolutionary graph generation (EGG) for automated circuit synthesis. The EGG system can be systematically implemented for different design problems by inheriting the framework class templates. The potential capability of EGG framework is demonstrated through experimental synthesis of both digital and analogue circuits. Design examples discussed in this paper are: (i) bit-serial multipliers using bit-level arithmetic components; and (ii) current mirrors using transistor-level components.

This paper presents a graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), to synthesize arithmetic circuits. The potential capability of EGG has been investigated through an experiment of synthesizing fast constant-coefficient multipliers.

This paper proposed an efficient human motion segmentation algorithm with pixel-wise accuracy. Our aim is to solve the problem of separating human image as object of interest from the background image. In our approach, every pixel of a video sequence frame is considered to be a 5-dimensional vector, consisting of pixel position coordinate components (x,y coordinates) plus pixel color information in HSV (Hue, Saturation, and Value). First, the human assistant is employed to create the reference frame of desired human object of interest. This step is done only at the first frame of video sequence. The Kohonen Learning Vector Quantization (LVQ) is then used to give optimal class region decision between the human object class and background class by training its codebook vectors, supervised by reference frame. The segmentation result is generated by doing vector quantization of LVQ codebook vectors to all pixels of image frame. Finally, for adapting the human object class movement in succeeding frames, LVQ codebook vectors are updated periodically by feeding back the result of the last segmentation into the training step. This paper also presents proposed segmentation algorithm performance to some MPEG-4 video test.

We present an efficient graph-based evolutionary optimization technique, called evolutionary graph generation (EGG), and the proposed approach is applied to the design of combinational and sequential arithmetic circuits based on parallel counter-tree architecture. The fundamental idea of EGG is to employ general circuit graphs as individuals and manipulate the circuit graphs directly using new evolutionary graph operations without encoding the graphs into other indirect representations, such as the bit strings used in genetic algorithm (GA) proposed by Holland (1992) and trees used in genetic programming (GP) proposed by Koza et al. (1997). In this paper, the EGG system is applied to the design of constant-coefficient multipliers and the design of bit-serial data-parallel adders. The results demonstrate the potential capability of EGG to solve the practical design problems for arithmetic circuits with limited knowledge of computer arithmetic algorithms. The proposed EGG system can help to simplify and speed up the process of designing arithmetic circuits and can produce better solutions to the given problem.

The paper presents a hardware algorithm for a real/complex reconfigurable arithmetic unit, which can change its structure for three different arithmetic modes in real time. The three modes realize: (i) a single precision complex number multiplication; (ii) a double precision real number multiplication; and (iii) a pair of single precision real number four operand multiply-add operations, respectively. We discuss the reconfiguration of hardware structure on the basis of the transformation of the number system used in each arithmetic mode. The designed arithmetic unit can perform high speed real/complex arithmetic computations based on binary tree addition scheme, and also exhibits highly regular structure suited for VLSI implementation.