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James D. Bargainer

dblp:66/3322 · DBLP profile ↗
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3ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 2 · 1 first-authorComputer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 83% Integrated circuit design · 17%
Theoretical computer science
1 paper
Automata and formal languages · 100%
Computer graphics and multimedia
1 paper
Image and video coding · 100%

Topics — the 9 heaviest of 10, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
hardware verification and test
0.011975
An Improved Bound for Checking Experiments that Use Simple Input-Output and Characterizing Sequences · IEEE Trans. Computers 1975
Automata and formal languages › finite automata › finite state machine testing
checking experiments
0.011975
An Improved Bound for Checking Experiments that Use Simple Input-Output and Characterizing Sequences · IEEE Trans. Computers 1975
Automata and formal languages
finite automata
0.011975
An Improved Bound for Checking Experiments that Use Simple Input-Output and Characterizing Sequences · IEEE Trans. Computers 1975
Electronic design automation › logic synthesis
boolean function realization
0.011970
R70-34 Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic · IEEE Trans. Computers 1970
Electronic design automation
logic synthesis
0.011970
R70-34 Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic · IEEE Trans. Computers 1970
Integrated circuit design › digital circuit design
threshold logic
0.011970
R70-34 Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic · IEEE Trans. Computers 1970
Electronic design automation › logic synthesis
threshold logic synthesis
0.011970
R70-34 Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic · IEEE Trans. Computers 1970
Image and video coding
quantization
0.011977
A Linear Algorithm for the Merli Scan · IEEE Trans. Commun. 1977
Automata and formal languages › finite automata
finite state machine testing
0.011975
An Improved Bound for Checking Experiments that Use Simple Input-Output and Characterizing Sequences · IEEE Trans. Computers 1975

Methods — techniques the papers use, named apart from their topics

linear algorithm design · 0.0tree method · 0.0geometric methods · 0.0algebraic methods · 0.0
YearPublicationVenuePosition
1977 A Linear Algorithm for the Merli Scan
abstract
A linear algorithm for the merli scan is described which exhibits a better quantization SNR than a nonlinear algorithm proposed by Limb and is more easily implemented. The error propagation characteristics for the linear algorithm are similar to those for the Limb algorithm.
A. Ramirez, Richard Simpson 0001, G. W. Batten, James D. Bargainer
IEEE Trans. Commun.4
1975 An Improved Bound for Checking Experiments that Use Simple Input-Output and Characterizing Sequences
abstract
The least upper bound of n(n−1)/2 input symbols is derived for the total length of characterizing sequences for a reduced n-state machine. When a machine can be characterized by a set of r characterizing sequences, a reduced upper bound on their total length will be r(2n−r−1)/2 input symbols. To shorten transfer sequences, better use is made of the strong-connectedness assumptions of the machines to be tested. The reduced bounds on characterizing and transfer sequences are utilized to improve the upper bounds on checking experiments employing simple input/output (I/O) sequences.
Theodore T. Tylaska, James D. Bargainer
IEEE Trans. Computers2
1970 R70-34 Unateness Test of a Boolean Function and Two General Synthesis Methods Using Threshold Logic
abstract
The problem treated in this paper is that of realizing a Boolean function which is not linearly separable with a network of threshold gates. This problem has been treated by the tree method of Coates and Lewis [1], the geometric methods of Winder [5], and the algebraic methods of Hopcroft and Mattson [3] and Stabler [4] among others. In the above methods, the techniques become computationally impractical for a large number of variables and functions requiring several threshold gates. The method presented in this paper suffers from the same limitations, as well as from the fact that it is based entirely on necessary but not sufficient conditions for linear separability.
James D. Bargainer
IEEE Trans. Computers1