We review behavioral and RTL test synthesis and synthesis for testability approaches that generate easily testable implementations. We also include an overview of high-level synthesis techniques to assist high-level ATPG.

Digital clock pulse control elements - delay lines and pulse-shaping elements - are used widely for clock generation and clock tuning in synchronous digital logic. However, they are intrinsically redundant circuits: without special modifications, DC logic testing cannot completely verify their static behavior (including the correct operation of the decoders and selectors used for their programming and control). This paper demonstrates low overhead circuit modification techniques that can be applied to all classes of programmable clock control elements, ensuring their complete single stuck-at fault testability.>

Board test using functioiial self-test code can be augmented by concurrently sampling signals at chip boundaries, compressing this data, and verifying its signature in-line in the code. This is a general method to enhance board test and diagnosis, po1,erXtidy adding every chip J/O pin as an observation point that is observed frequently and coupled to the self-test. Tests continue to execute at the normal board operating speed. This combination of fnnctional and strudural testing offers improved effectiveness over functional testing alone.

A starting point for a set of design for testability (DFT) principles that can be used with mixed signal integrated circuits is presented. The authors argue that an effective DFT technique should enhance the ability to perform digital signal processing and other modern test techniques on analog macros embedded in the integrated circuit, since quality will be a driving force with increasing integration. The proposed test methodology consists of (1) establishing the digital test model for testing of digital logic and (2) establishing the analog test mode and each of the submodes (called test configurations) for serial or parallel testing of analog partitions. Digital and analog circuitry must be isolated from each other, i.e. an uncontrolled analog signal must not be able to affect the digital test mode and vice versa.>

A probabilistic model for pseudorandom testing of combinational circuits is presented. The expected fault coverage is shown to be accurately approximated as a series of exponentials that depends on the test length and the fault detectabilities. The derivations do not require the pattern generator to have the same number of stages as there are network inputs.>

Algorithmic test generation for high fault coverage is an expensive and time-consuming process. As an alternative, circuits can be tested by applying pseudorandom patterns generated by a linear feedback shift register (LFSR). Although no fault simulation is needed, analysis of pseudorandom testing requires the circuit detectability profile.