The science gateway nanoHUB.org is the world's largest nanotechnology user facility, serving 167, 196 users in 2010 with over 2,300 resources including 189 simulation programs. Surveys of nanoHUB users and automated usage analysis find widespread simulation use in formal classroom education, thereby connecting recent research more rapidly and closely to education. Analysis of 719 citations in the scientific literature by over 1,300 authors to nanoHUB.org resources documents use of simulation programs by new research collaborations, by researchers outside of the community originating the program, and by experimentalists. The publication and author networks reveal research collaborations and capacity building through knowledge transfer. Analysis of secondary citations documents the quality of the conducted research with an h-index of 30 after just 10 years of operation. Our analysis proves with quantitative metrics that impactful research can be conducted by an ever growing research community. We argue that HUBzeroTM technology and the user-focused design and operation of nanoHUB.org are keys to success that can be transferred to other science gateways.

Stack filters are a class of nonlinear filters with excellent properties for signal restoration. Unfortunately, present algorithms for designing stack filters can only be used for small window sizes because of either their computational overhead or their serial nature. This paper presents a new adaptive algorithm for determining a stack filter that minimizes the mean absolute error criterion. The new algorithm retains the iterative nature of many current adaptive stack filtering algorithms, but significantly reduces the number of iterations required to converge to an optimal filter. This algorithm is faster than all currently available stack filter design algorithms, is simple to implement, and is shown in this paper to always converge to an optimal stack filter. Extensive comparisons between this new algorithm and all existing algorithms are provided. The comparisons are based both on the performance of the resulting filters and upon the time and space complexity of the algorithms. They demonstrate that the new algorithm has three advantages: it is faster than all other available algorithms; it can be used on standard workstations (SPARC 5 with 48 MB) to design filters with windows containing 20 or more points; and, its highly parallel structure allows very fast implementations on parallel machines. This new algorithm allows cascades of stack filters to be designed; stack filters with windows containing 72 points have been designed in a matter of minutes under this new approach.

DS (Decoupled-Superscalar) is a new microarchitecture that combines decoupled and superscalar techniques to exploit instruction level parallelism. Issue bandwidth is increased while circuit complexity growth is controlled with little negative impact on performance. Programs for DS are compiled into two instruction substreams: the dominant substream navigates the control flow and the rest of computational task is shared between the dominant and subsidiary substreams. Each substream is processed by a separate superscalar core realizable with current VLSI technology. DS machines are binary compatible with superscalar machines having the same instruction set, and a family of DS machines is binary compatible without recompilation. DS run time behavior is examined with an analytical model. A novel technique for controlling slip between substreams is introduced. Code partitioning issues of instruction count balancing and residence time balancing, important to any split-stream scheme, are discussed. Simulation shows DS achieves performance comparable to an aggressive superscalar, but with potentially less complex hardware and faster clock rate.

No abstract available.

Recent simulation based studies suggest that while superpipelines and superscalars are equally capable of exploiting fine grained concurrency, multiprocessors are better at exploiting coarse grained parallelism. An analytical model that is more flexible and less costly in terms of run time than simulation, is proposed as a tool for analyzing the tradeoff between superpipelined processors, superscalar processors, and multiprocessors. The duality of superpipelines and superscalars is examined in detail. The performance limit for these systems has been derived and it supports the fetch bottleneck observation of previous researchers. Common characteristics of utilization curves for such systems are examined. Combined systems, such as superpipelined multiprocessors and superscalar multiprocessors, are also analyzed. The model shows that the number of pipelines (or processors) at which the maximum throughput is obtained is, as memory access time increases, increasingly sensitive to the ratio of memory access time to network access delay. Further, as a function of interiteration dependence distance, optimum throughput is shown to vary nonlinearly, whereas the corresponding optimum number of processors varies linearly. The predictions from the analytical model agree with similar results published using simulation based techniques.>

When the instruction level parallelism exceeds the available machine parallelism, a decision must be made as to which instructions get priority. This paper investigates the performance potential of five dynamic scheduling algorithms to prioritize instructions beyond basic blocks, thereby increasing processor utilization and performance. Trace-driven simulations for six benchmarks are used to analyze scheduling performance. A unique pipelining approach is introduced to address implementation limitations.>

Several recent parallel computers have implemented logically shared, physically distributed memory systems which allow processors to directly access memory in other processors without interrupting the referenced processing element. Because this kind of architecture provides greater flexibility for interprocessor communications than private address space computers, different software models can be developed to take advantage of these machines. In this paper, we describe a low-level collective communications interface called SLICC (Shared address-space Library Interface for Collective Communications), that is specifically tailored for shared memory parallel computers. We also provide performance results for an implementation on the Cray T3D and compare its performance to Cray's PVM implementation. These results show that SLICC can be more than 10 times faster than PVM on the T3D.>

Detecting independent operations is a prime objective for computers that are capable of issuing and executing multiple operations simultaneously. The number of instructions that are simultaneously examined for detecting those that are independent is the scope of concurrency detection. The authors present an analytical model for predicting the performance impact of varying the scope of concurrency detection as a function of available resources, such as number of pipelines in a superscalar architecture. The model developed can show where a performance bottleneck might be: insufficient resources to exploit discovered parallelism, insufficient instruction stream parallelism, or insufficient scope of concurrency detection. The cost associated with speculative execution is examined via a set of probability distributions that characterize the inherent parallelism in the instruction stream. These results were derived using traces from a Multiflow TRACE SCHEDULING compacting FORTRAN 77 and C compilers. The experiments provide misprediction delay estimates for 11 common application-level benchmarks under scope constraints, assuming speculative, out-of-order execution and run time scheduling. The throughput prediction of the analytical model is shown to be close to the measured static throughput of the compiler output.>

The Augmented Data Manipulator (ADM) network has been proposed as an interconnection network for SIMD machines. As one measure for comparing the ADM network to multistage cube networks, the number of distinct data permutations performable in a single pass through the ADM is examined. Techniques are given to count the number of settings of any stage of the network which are permutations. Upper and lower bounds on the number of distinct permutations performable by the network are proven.

The Extra Stage Cube (ESC) interconnection network, a fault-tolerant structure, is proposed for use in large-scale parallel and distributed supercomputer systems. It has all of the interconnecting capabilities of the multistage cube-type networks that have been proposed for many supersystems. The ESC is derived from the Generalized Cube network by the addition of one stage of interchange boxes and a bypass capability for two stages. It is shown that the ESC provides fault tolerance for any single failure. Further, the network can be controlled even when it has a failure, using a simple modification of a routing tag scheme proposed for the Generalized Cube. Both one-to-one and broadcast connections under routing tag control are performable by the faulted ESC. The ability of the ESC to operate with multiple faults is examined. The ways in which the ESC can be partitioned and permute data are described.