This review provides an overview of the placement function within automatic layout systems. The automatic placement problem is defined and the data abstractions are described. The discussion divides placement algorithms into two classes: constructive and iterative. Applications of the algorithms within layout systems are described. A large number of references is provided to allow use as a guide to placement literature.

The ultimate goal of all automated routing systems is to interconnect 100% of the necessary point-to-point electrical connections. However, most automated routing systems fail to find acceptable paths for all required connections because of limited routing resources or problem complexity. Therefore, a cleanup phase is often necessary. During this cleanup phase, connectivity can be improved through a variety of manual and automated techniques. This paper concentrates on one automated technique, rip-up and reroute. Various rip-up and reroute strategies are discussed and evaluated, and experimental results are provided.

CC-TEGAS3 is a digital logic simulation system containing subsystems which can perform three different modes of simulation. These modes are used for logic or design verification, worst case timing analysis, and fault simulation. The basic device models are for Boolean gates, a wide range of flip-flops and latches, and a number of MOS elements such as transfer gates. A comprehensive list of functional level device models were incorporated into the system and the resulting system is called CC-TEGAS4. This approach was considered advantageous for today's technology, and an absolute necessity for the LSI and VLSI technologies that are forthcoming. This paper is concerned with the problems encountered and some of the techniques used to implement these functional level models, and results obtained in terms of reduction in required computer resources needed to simulate a network utilizing these new models.