Demo Data from EDBT 2026 / reviewers in the wild / expert
Marshall C. Pease III
dblp:66/4084
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1977
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Parallel and multicore computing · 100% |
Topics — the 2 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Parallel and multicore computing › parallel architecture
microprocessor array |
0.0 | 1 | 1977 | The Indirect Binary n-Cube Microprocessor Array · IEEE Trans. Computers 1977 |
Parallel and multicore computing › parallel computation models
massively parallel computation |
0.0 | 1 | 1977 | The Indirect Binary n-Cube Microprocessor Array · IEEE Trans. Computers 1977 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1977 | The Indirect Binary n-Cube Microprocessor ArrayabstractThis paper explores the possibility of using a large-scale array of microprocessors as a computational facility for the execution of massive numerical computations with a high degree of parallelism. By microprocessor we mean a processor realized on one or a few semiconductor chips that include arithmetic and logical facilities and some memory. The current state of LSI technology makes this approach a feasible and attractive candidate for use in a macrocomputer facility. Marshall C. Pease III |
IEEE Trans. Computers | 1 |