Van and Houtte1have suggested a delayed ULM-n for synthesis of sequential machines. Almost an identical approach was suggested by Sureshchander and Bhatt [1] earlier.

An algorithm is presented in this correspondence which will generate only those prime implicants (PI's) which are essential or necessary for a minimal sum of products (the technique can be extended for product of sums form also) of a given switching function —iven all the minterms. This algorithm eliminates the neces-sity of finding out all the PI's.

An algorithm is described in this note to determine whether a switching function is asummable or not. The algorithm is efficient and simple for testing 2-asummability.

Some comments are offered on the number of I/O terminals p of the Q-universal logic modules (ULM) [2]. An equation is given in this note which will determine minimum number of I/O terminals for all n.

In this correspondence a new representation of a sequential machine (without output) is given which enables the determination of all incompatible pairs without any intermediate step(s). The method is programmable, is much faster, and requires less memory than existing methods.

Some comments are made on the above note,1to indicate that the decomposition relations used in this technique can be obtained in a much simpler way and to point out that the technique has been mentioned earlier in the literature.

In the above mentioned paper,1Perlman has given a method of state assignment of binary sequence detectors on the assumption that "the BSD represents a very special class of sequential networks and may be treated accordingly." (The BSD's are in fact a special class of networks, and their flow tables are much more ordered, resulting in a comparative ease in choosing an economical assignment.) It is suggested that the assignment be taken from BRS (binary ring sequence) such that 1) successive states through which the detector progresses when the sequence is entered are made to correspond to successive subsequences; 2) an initial state is chosen whereby one of a total of rmindelay units in the detector will track the input x at all times.

In view of the recent communication by Marcus [1], the rules for generation of various combinations of input equations for the RST flip- flop [2] can be modified as in Table 1.

In a recent paper Graham and Distler1have shown how all the possible combinations of the input equations of an RST flip-flop can be displayed simultaneously on the Karnaugh maps. This claim is valid only if a1, a2on the R map and a3, a4on the S map are replaced by ai, and each aican be chosen independently of the others. Whereas, in the Graham and Distler techniques, a1chosen to be 1 (or 0) on one vertex of the Karnaugh map implies that all a1are to be 1 (or 0), and the same is true about a2, a3, and a4.