In this note, we examine the problem of finding good state assignments when mixed memory type realizations (i.e., including mixtures of delay and trigger flip-flop memories) are permitted. Specifically, we describe situations that take advantage of this extra degree of design freedom, and we indicate how to modify two existing algorithms to determine such mixed realizations systematically.

This paper considers the problem of economical assignment of codes to the internal states of sequential circuits. The only restriction placed on these circuits is the fact that they are assumed to be clocked. The internal logic is realized with two-level diode or transistor circuitry, and the methods given here minimize both the number of gates and of gate inputs (diodes) required to realize a given sequential circuit. Methods are first developed for the coding of small fully specified state tables for which only the internal logic is to be minimized. These methods are then successively extended to cover the situations where it is desired to minimize simultaneously both the internal logic and the output logic of a sequential circuit, where the state tables are not fully specified, and where the size of the state tables is arbitrarily large. A method for dealing with the special class of ``counter-like'' state tables is also given. All the procedures presented here are designed to be easily programmable on a digital computer, and several of these methods have been so programmed. Our methods are discussed and compared with other existing procedures.