In this paper we present two new Non Data Aided (NDA) phase detectors (PDs) for carrier synchronization Phase Locked Loops (PLLs) in M-ary Phase Shift Keying (M-PSK) receivers. The first structure is a self-normalizing modification of the M-th order nonlinearity detector. We investigate this detector theoretically in order to predict its S-curve, self-noise, squaring-loss, and phase-error variance performance. These theoretical predictions are then verified by computer simulations, and the results are contrasted with results obtained using other NDA and Decision Directed (DD) phase detectors. As those comparisons show, the proposed structure offers improved phase-error variance performance that is robust to Automatic Gain Control (AGC) circuit imperfections. Moreover, the new detector has a compact hardware structure suitable for implementation within an FPGA or ASIC. The second phase detector structure presented is an adaptive detector whose principal novelty is that it dynamically adapts the phase detector's gain to allow the PLL to perform optimally at any input Signal-to-Noise Ratio (SNR) at which it can lock. This detector is also robust vis-a-vis the AGC and has a compact hardware implementation suitable for FPGAs and ASICs.

We present a novel method for travel-time measurement for geophysical inversion problems. Instead of computing travel-times through measurement of the propagation delay of a "one-shot" disturbance sent between a source-receiver pair (the "conventional" approach), in our system we establish a continuous spread-spectrum acoustical communications link between the source and the receiver. Then, we send over this link time-stamped data that, when recovered at the receiver, facilitates travel-time measurement. The principal novelty of our approach is that the problem of eliminating the effects of unwanted wave reflections and refractions which arrive at the receiver is transformed into the problem of reducing multipath interference in a spread-spectrum communications system, a topic which has been the subject of extensive research over recent years and for which many proven techniques are available. In this paper we present the theory behind our approach, as well as simulation results obtained through use of a simulation program developed by the authors.

This paper presents a new lock detector structure for symbol timing recovery PLLs (Phase Lock Loops), which operate in QPSK. (Quaternary Phase Shift Keying) and BPSK (Binary Phase Shift Keying) receivers in AWGN (Additive White Gaussian Noise) channels. The lock detector requires only 2 samples/symbol, which coincide with those required for the Gardner timing error detector. Simulation results are used to characterize the detector's behavior quantitatively. Both rectangular and square-root raised-cosine baseband data pulses are treated. It emerges that the lock detector has two very useful qualities. First, it is self-normalizing, and, secondly, the channel E/sub S//N/sub 0/ ratio can be easily determined from its value when the receiver is locked. Finally, a simple hardware structure is found for the lock metric computation process, which allows for its efficient implementation within an FPGA (Field Programmable Gate Array) or ASIC (Application Specific Integrated Circuit).

A new method of estimating the signal-to-noise ratio for M-PSK receivers was presented previously, which derives that estimate from the locked-state value of a new family of carrier lock detectors. A quantitative analysis is undertaken in which it is shown that this method requires significantly less hardware and/or software resources than estimation from the received signal's error rate, is irrespective of the data sequence, and necessitates far fewer symbols in order to arrive at an equally accurate estimate.

A family of carrier lock detectors for M-PSK receivers operating in additive white Gaussian noise channels is suggested. The statistical properties of the lock detectors are derived theoretically using stochastic analysis, and computer simulations are used to validate the results obtained. The derivations yield discovery of two useful attributes of the lock detectors: 1) they are self-normalizing (or in other words signal-level independent) and 2) the channel E/sub S//N/sub 0/ can be readily ascertained from the lock metric when the receiver is in lock. Furthermore, a particularly simple hardware implementation for the lock metric computation process is found, which allows easy and efficient implementation of its computation within a field programmable gate array (FPGA) or application specified integrated circuit (ASIC). Analysis of the lock detectors' behavior under imperfect locking conditions is also discussed, and simulation results are presented. An overview is given of the applicability of the lock detectors to several related digital phase modulation schemes.