We provide an improved assessment of Google Brain’s deep reinforcement learning approach to macro placement [29] and its updated Circuit Training (CT) implementation in GitHub [53]. A stronger simulated annealing (SA) baseline leverages the “go-with-the-winners” metaheuristic [3] and a multi-threading implementation. We develop and release new public benchmarks in sub-10nm technology: LEF/DEF for Google’s 7nm TSMC Ariane protobuf and scaled variants, as well as testcases implemented in the open-source ASAP7 7nm research enablement. We evaluate from-scratch training and fine-tuning results for the latest “AlphaChip” release of Circuit Training, alongside multiple alternative macro placers. We also study the recently-published pre-training guidance in [53]. A commercial place-and-route tool is used to provide “true reward” post-route power, performance and area metrics. All data, evaluation flows and related scripts are publicly available in theMacroPlacementGitHub repository [63]. Our study affords insights into reproducibility and reporting in the research literature, and points out still-missing confirmations (e.g., of CT’s scalability and pre-training methodology) that remain open questions for the research community.

With the growing demand for VLSI scaling, standard cell library generation becomes crucial process to enhance performance via design technology co-optimization (DTCO) and system technology co-optimization (STCO) exploration. In this work, we review existing methodologies and algorithms used for standard cell layout automation for sub-10nm nodes, categorized by their algorithmic approaches for transistor placement and internal cell routing.

Moore's law scaling is approaching physical limits, as indicated by the technology roadmap. Recent standard cell layout reductions rely on track height compression, which increases pin density and routing congestion. To address these challenges, design technology co-optimization (DTCO) was introduced. This paper explores how much track height can be compressed and how DTCO features can sustain layout scaling. To support this exploration, we developed an SMT-based cell synthesis tool that integrates gear ratio, M1 metal grid offset, local-interconnect source-drain (LISD) merging, adjustable gate cut lengths, and double-height architecture with pass-throughs, and various power delivery options.

As physical pitch scaling slows, efforts to match its pace by reducing standard cell height and sacrificing horizontal routing tracks have introduced placement and routing challenges, making the design of high-quality standard cell layouts increasingly crucial. However, existing cell metrics only focus on pin accessibility and are insufficient to address issues in advanced nodes (e.g., Power Delivery Networks (PDN), increased routing blockages, etc.). We propose Cell Layout Flexibility(Cell-Flex) metrics, novel metrics that evaluate flexibility of standard cell layouts. flexibility reflects the versatility of cell layouts to placement and routing demands, which influences optimizing block design. By using Cell-Flex metrics as objectives in designing cell layout, we achieve a 13.2% reduction in block area without increasing total Design Rule Violations (DRVs). We develop a Machine Learning (ML) model using Kolmogorov-Arnold Networks (KAN) that utilizes the Cell-Flex metrics as features to make DRV prediction. By adding Cell-Flex features, we improve accuracy from 0.65 to 0.79 and F1 score from 0.52 to 0.78, demonstrating that our metrics are important for DRV prediction and serve as robust indicators of cell layout quality.

State-of-the-art analytical placement algorithms for VLSI designs rely on solving nonlinear programs to minimize wirelength and cell congestion. As a consequence, the quality of solutions produced using these algorithms crucially depends on the initial cell coordinates. In this work, we reduce the problem of finding wirelength-minimal initial layouts subject to density and fixed-macro constraints to a Quadratically Constrained Quadratic Program (QCQP). We additionally propose an efficient sequential quadratic programming algorithm to recover a block-globally optimal solution and a subspace method to reduce the complexity of problem. We extend our formulation to facilitate direct minimization of the Half-Perimeter Wirelength (HPWL) by showing that a corresponding solution can be derived by solving a sequence of reweighted quadratic programs. Critically, our method is parameter-free, i.e. involves no hyperparameters to tune. We demonstrate that incorporating initial layouts produced by our algorithm with a global analytical placer results in improvements of up to 4.76% in post-detailed-placement wirelength on the ISPD'05 benchmark suite. Our code is available on github. https://github.com/choltz95/laplacian-eigenmaps-revisited.

We provide open, transparent implementation and assessment of Google Brain's deep reinforcement learning approach to macro placement (Nature) and its Circuit Training (CT) implementation in GitHub. We implement in open-source key "blackbox" elements of CT, and clarify discrepancies between CT and Nature. New testcases on open enablements are developed and released. We assess CT alongside multiple alternative macro placers, with all evaluation flows and related scripts public in GitHub. Our experiments also encompass academic mixed-size placement benchmarks, as well as ablation and stability studies. We comment on the impact of Nature and CT, as well as directions for future research.

Canonical methods for analytical placement of VLSI designs rely on solving nonlinear programs to minimize wirelength and cell overlap. We focus on producing initial layouts such that a global analytical placer performs better compared to existing heuristics for initialization. We reduce the problem of initialization to a quadratically constrained quadratic program. Our formulation is aware of fixed macros. We propose an efficient algorithm which can quickly generate initializations for testcases with millions of cells. We show that the our method for parameter initialization results in superior performance with respect to post-detailed placement wirelength.