The AUTOSAR standard is the predominant architecture for the development of automotive industrial software. AUTOSAR allows the generation of software components which can be re-utilized in several platforms with different underlying hardware. However the adoption of AUTOSAR as a main subject within the academy has been aggravated by the strong dependency on highly expensive AUTOSAR vendors (e.g., generation tools, stacks, etc.) which are needed for the easy configuration and generation of AUTOSAR-compliant software. In this paper we introduce the concept of an AUTOSAR classic demonstrator as part of the AUTOSAR university package. This AUTOSAR classic demonstrator is based on open source AUTOSAR modules and software tools which minimizes the costs for a real implementation during teaching lectures as well as for the evaluation of new concepts and features within the AUTOSAR classic standard.

The complexity of vehicle applications and the need of reducing the number of processing units are giving great audience to system virtualization. Virtualized architectures with diverse Automotive Safety Integrity Level (ASIL) in the same multicore hardware, known as Mixed Criticality Systems (MCSs), offer flexibility but are extremely challenging in terms of timing validation and resources partitioning. At the same time, RISC- V technologies are becoming central in automotive thanks to open source licensing and customizable solutions. However, most of these architectures cannot sustain MCSs for the absence of features that can be performed only through hardware extensions. In this paper we define details and show a preliminary design and synthesis of a Programmable PMU (PPMU). In virtual systems an extension reporting hardware performance is essential to absolve timing analysis and shared resources balancing purposes. Moreover, in the paper we present a table containing major Hardware Events (HEs) we are interested in, and that can be monitored. The HEs are classified by the role they have in a MCS: Functional Safety (FuSa) analysis or Performance analysis. The synthesis of the PPMU highlighted that the device introduces a limited hardware overhead, e.g. in the worst case the unit uses less than 3 % of available programmable logic of a xczu9eg FPGA device.

The high-performance requirements needed to implement the most advanced functionalities of current and future Cyber-Physical Systems (CPSs) are challenging the development processes of CPSs. On one side, CPSs rely on model-driven engineering (MDE) to satisfy the non-functional constraints and to ensure a smooth and safe integration of new features. On the other side, the use of complex parallel and heterogeneous embedded processor architectures becomes mandatory to cope with the performance requirements. In this regard, parallel programming models, such as OpenMP or CUDA, are a fundamental brick to fully exploit the performance capabilities of these architectures. However, parallel programming models are not compatible with current MDE approaches, creating a gap between the MDE used to develop CPSs and the parallel programming models supported by novel and future embedded platforms.The AMPERE project will bridge this gap by implementing a novel software architecture for the development of advanced CPSs. To do so, the proposed software architecture will be capable of capturing the definition of the components and communications described in the MDE framework, together with the non-functional properties, and transform it into key parallel constructs present in current parallel models, which may require extensions. These features will allow for making an efficient use of underlying parallel and heterogeneous architectures, while ensuring compliance with non-functional requirements, including those on real-time performance of the system.

Stack sharing between tasks may significantly reduce the amount of memory required in resource-constrained real-time embedded systems. Existing work on stack sharing mainly focused on stack sharing between tasks that neither leave any data on the stack from one instance to another nor suspend themselves, i.e. tasks with a so-called single-shot execution. In this paper, we consider stack memory requirements of AUTOSAR/OSEK-compliant scheduling policies for a mixed task set, consisting of so-called basic and extended tasks. Unlike basic tasks, that have a single-shot execution, extended tasks are allowed to leave data on the stack from one instance to another and to suspend themselves. We prove that minimizing the shared stack requirement for such a mixed task set is an NP-hard problem. We subsequently provide an heuristic-based algorithm to minimize stack usage of a mixed task set, and evaluate the algorithm through a case study of an implementation of an unmanned aerial vehicle. An extended version of the paper is available as technical report [5].

Stack sharing between tasks may significantly reduce the amount of memory required in resource-constrained real-time embedded systems. On the downside, stack sharing decreases the predictability of a system, e.g. may give rise to a substantial variation in the address space for the memory locations used for the stack of a task. As a result, the precision of execution-time bounds may be reduced, the pessimism in schedulability analysis increased, and optimizations to increase schedulability hampered. In this paper, we present EMPRESS, an Efficient and effective Method for PREdictable Stack Sharing. We assume priority-based scheduled systems, where the binary pre-emption relation on tasks is a strict partial order, and static bounds on each task's stack usage. Both assumptions are common in the embedded real-time domain. For such systems, EMPRESS provides a predictable stack sharing between tasks, i.e. the stack of every task is always located in the very same memory area, even for tasks sharing a stack. It therefore combines the predictability of dedicated stack spaces with the reduced memory need of a shared stack. We exemplify the benefits of EMPRESS using as a case study an implementation of an unmanned aerial vehicle, and explain how EMPRESS can be realized within t.he Erika Enterprise RTOS without additional overheads.

The flexible spin-lock model (FSLM) unifies suspension-based and spin-based resource access protocols for partitioned fixed-priority preemptive scheduling based real-time multi-core platforms. Recent work has been done in defining the protocol for FSLM, providing schedulability analysis, and investigating the practical consequences of the theoretical model. FSLM complies to the AUTOSAR standard for the automotive industry, and prototype implementations of FSLM in the OSEK/VDX-complaint Erika Enterprise Real-Time Operating System have been realized. In this paper, we briefly describe some practical challenges to improve efficiency and generality.

The flexible spin-lock model (FSLM) unifies suspension-based and spin-based resource sharing protocols for partitioned fixed-priority preemptive scheduling based real-time multiprocessor platforms. Recent work has been done in defining the protocol for FSLM and providing a schedulability analysis without accounting for the implementation overheads. In this paper, we extend the analysis for FSLM with implementation overheads. Utilizing an initial implementation of FSLM in the OSEK/VDX-compliant Erika Enterprise RTOS on an Altera Nios II platform using 4 soft-core processors, we present an improved implementation. Given the design of the implementation, the overheads are characterized and incorporated in specific terms of the existing analysis. The paper also supplements the analysis with measurement results, enabling an analytical comparison of FSLM with the natively provided multiprocessor stack resource policy (MSRP), which may serve as a guideline for the choice of FSLM or MSRP for a specific application.

The advent of commercial-of-the-shelf (COTS) heterogeneous many-core platforms is opening up a series of opportunities in the embedded computing market. Integrating multiple computing elements running at lower frequencies allows obtaining impressive performance capabilities at a reduced power consumption. These platforms can be successfully adopted to build the next-generation of self-driving vehicles, where Advanced Driver Assistance Systems (ADAS) need to process unprecedently higher computing workloads at low power budgets. Unfortunately, the current methodologies for providing real-time guarantees are uneffective when applied to the complex architectures of modern many-cores. Having impressive average performances with no guaranteed bounds on the response times of the critical computing activities is of little if no use to these applications. Project HERCULES will provide the required technological infrastructure to obtain an order-of-magnitude improvement in the cost and power consumption of next generation automotive systems. This paper presents the integrated software framework of the project, which allows achieving predictable performance on top of cutting-edge heterogeneous COTS platforms. The proposed software stack will let both real-time and non real-time application coexist on next-generation, power-efficient embedded platform, with preserved timing guarantees.

Multi-core is a game changer for automotive industry, providing unprecedented computing capabilities, and allowing consolidating heterogeneous applications into a single device with benefits in terms of cost and reuse. Multi-core asks for virtualization of applications, moving from the hardware-centric perspective to the function-centric perspective: applications on a single electronic control unit (ECU) are transformed into hardware-agnostic functionalities that hosted by multicore ECUs alongside other, unrelated, applications. Moreover, to exploit multi-cores to the full extent in some automotive applications, the guarantee is needed that different applications exposing different criticalities (e.g., ISO26262 ASIL D and ISO26262 ASIL B) can coexist. The paper presents the technologies available to support these concepts such as AUTOSAR and embedded virtualizations, presenting the main issues that have to be solved and discussing the state of the art.

People and objects will soon share the same digital network for information exchange in a world named as the age of the cyber-physical systems. The general expectation is that people and systems will interact in real-time. This poses pressure onto systems design to support increasing demands on computational power, while keeping a low power envelop. Additionally, modular scaling and easy programmability are also important to ensure these systems to become widespread. The whole set of expectations impose scientific and technological challenges that need to be properly addressed. The AXIOM project (Agile, eXtensible, fast I/O Module) will research new hardware/software architectures for cyber-physical systems to meet such expectations. The technical approach aims at solving fundamental problems to enable easy programmability of heterogeneous multi-core multi-board systems. AXIOM proposes the use of the task-based OmpSs programming model, leveraging low-level communication interfaces provided by the hardware. Modular scalability will be possible thanks to a fast interconnect embedded into each module. To this aim, an innovative ARM and FPGA-based board will be designed, with enhanced capabilities for interfacing with the physical world. Its effectiveness will be demonstrated with key scenarios such as Smart Video-Surveillance and Smart Living/Home (domotics).

The adoption of AUTOSAR in the development of automotive electronics can increase the portability and reuse of functional components. Inside each component, the behavior is represented by a set of runnables, defining reactions executed in response to an event or periodic computations. The implementation of AUTOSAR runnables in a concurrent program executing as a set of tasks reveals several issues and trade-offs because of the need to protect communication and state variables and to ensure time determinism. We discuss some of these tradeoffs and options and outline a problem formulation that can be used to compute the solution with minimum memory requirements executing within the deadlines.

In industrial contexts it might be useful to deploy Wireless Sensor Networks to constantly monitor the status of a plant. At early design stage of any monitoring application, it is envisaged to reinforce real-time paradigms both for task execution and node- to-node communication. Model driven applications are usually seamless provided the system description is complete and robust, and the code generation (platform specific) appropriately complies with the model. We present a demo where acceleration measurements gathered by sensor nodes are conveyed to a fixed location devoted to surveillance. A higher level control system or an operator can take action whenever these readings deviate from the expected behavior. We follow a model-based implementation of the system exploiting the Scilab/Scicos support for the ERIKA Enterprise real-time kernel. Timeliness at the node level is reinforced by the features of the kernel scheduler; moreover the recent implementation of the IEEE 802.15.4 wireless communication standard permits time bounded communications among the nodes.

This paper presents a toolsuite for rapid prototyping and implementation of real-time applications on Wireless Sensor Networks. The work is motivated by the need to use WSNs in industrial control contexts, where the sampling rate, the workload is much higher than typical current applications of WSNs, and the real-time constraints are much tighter. We present a simulator for early evaluation of the real-time behavior of a WSN application; and a realtime operating system that implement appropriate real-time scheduling policies to allow timing analysis and guarantee timing constraints. We provide a demo based on a simple but realistic network scenario showing that simulation is in agreement with experimental results.

Ethernet was not originally developed to meet the requirements of real-time industrial automation systems and it was commonly considered unsuited for applications at the field level. Hence, several techniques were developed to make this protocol exhibit real-time behavior, some of them requiring specialized hardware, others providing soft-real-time guarantees only, or others achieving hard real-time guarantees with different levels of bandwidth efficiency. More recently, there has been an effort to support quality-of-service (QoS) negotiation and enforcement but there is not yet an Ethernet-based data link protocol capable of providing dynamic QoS management to further exploit the variable requirements of dynamic applications. This paper presents the FTT-Ethernet protocol, which efficiently supports hard-real-time operation in a flexible way, seamlessly over shared or switched Ethernet. The FTT-Ethernet protocol employs an efficient master/multislave transmission control technique and combines online scheduling with online admission control, to guarantee continued real-time operation under dynamic communication requirements, together with data structures and mechanisms that are tailored to support dynamic QoS management. The paper includes a sample application, aiming at the management of video streams, which highlights the protocol's ability to support dynamic QoS management with real-time guarantees.

Next generation embedded systems will demand applications with increasing complexity, so a standard uniprocessor microcontroller architecture will likely be unsuited to support. A possible solution to cope with embedded applications with high computational requirements is to adopt multiple-processor-on-a-chip architectures. The paper discusses the problem of multiprocessor scheduling for asymmetric architectures composed of a general purpose CPU and a DSP. The challenging issue addressed in this work is to verify whether the use of a dedicated processor can effectively enhance the performance of an embedded system, still maintaining some kind of real-time guarantee. In particular, we provide a method for increasing the schedulability bound in the considered architecture, allowing a more efficient use of the computational resources.

Despite having been designed to interconnect office equipment such as computers and printers, since its early daysEthernet has also been considered for use in the industrial domain. However, it was not originally developed to meet the requirements of real-time industrial automation systems and it was commonly considered unsuited for applications at the field level, i.e.to interconnect sensors, actuators and controllers. Therefore, along its 30 years of existence, several proposals have been presented to make this protocol exhibit real-timebehaviour. Nevertheless, these proposals either require specialised hardware, or are suited to soft-real-time operation only, or are bandwidth or response-time inefficient. This paper presents an overview about the work previously done towards real-time communication on Ethernet. Then, it presents a new protocol, FTT-Ethernet, which relies on common network adapters and on a new transmission control named master/multi-slave that efficiently supports hard-real-time operation in a flexible way.

This paper presents a dynamic configurable kernel architecture designed for supporting a simple implementation, integration and evaluation of scheduling algorithms. The main goal of the proposed architecture is to provide a platform for fast prototyping scheduling algorithms both for the CPU and for the devices. The kernel is fully modular in terms of scheduling policies, aperiodic servers, and concurrency control protocols, allowing applications to be developed independently from a particular system configuration. Finally, the system is compliant with the POSIX 1003.13 PSE52 specifications to simplify porting of application code developed for other POSIX compliant kernels.

The research on real-time software systems has produced algorithms that allow to effectively schedule system resources while guaranteeing the deadlines of the application and to group tasks in a very short number of non-preemptive sets which require much less RAM memory for stack. Unfortunately, up to now the research focus has been on time guarantees rather than the optimization of RAM usage. Furthermore, these techniques do not apply to multiprocessor architectures which are likely to be widely used in future microcontrollers. This paper presents a fast and simple algorithm for sharing resources in multiprocessor systems, together with an innovative procedure for assigning preemption thresholds to tasks. This allows to guarantee the schedulability of hard real-time task sets while minimizing RAM usage. The experimental part shows the effectiveness of a simulated annealing-based tool that allows to find a near-optimal task allocation. When used in conjunction with our preemption threshold assignment algorithm, our tool further reduces the RAM usage in multiprocessor systems.