To issue early warnings and rapidly initiate disaster responses after tsunami damage, various tsunami inundation forecast systems have been deployed worldwide. Japan's Cabinet Office operates a forecast system that utilizes supercomputers to perform tsunami propagation and inundation simulation in real time. Although this real-time approach is able to produce significantly more accurate forecasts than the conventional database-driven approach, its wider adoption was hindered because it was specifically developed for vector supercomputers. In this paper, we migrate the simulation code to modern CPUs and GPUs in a minimally invasive manner to reduce the testing and maintenance costs. A directive-based approach is employed to retain the structure of the original code while achieving performance portability, and hardware-specific optimizations including load balance improvement for GPUs are applied. The migrated code runs efficiently on recent CPUs, GPUs and vector processors: a six-hour tsunami simulation using over 47 million cells completes in less than 2.5 minutes on 32 Intel Sapphire Rapids CPUs and 1.5 minutes on 32 NVIDIA H100 GPUs. These results demonstrate that the code enables broader access to accurate tsunami inundation forecasts.

Cloud bursting functionality provides the administrators of on-premise supercomputing systems with an on-demand way of dynamically integrating the computing resources on the cloud into them when the computing demands from the users dramatically increase. In the Cybermedia Center at Osaka University, we have deployed a cloud bursting environment between a supercomputing system named SQUID and Microsoft Azure by respecting the transparency in usage rather than performance. Technically, the transparency allows users to execute their jobs on the cloud computing resources without having to be aware of the cloud in terms of usage. However, how we encourage users of our supercomputing system to use the cloud computing resources is a realistic and important problem to be solved from a practical operational perspective. In this paper, we investigate the cloud bursting environment on SQUID in terms of performance, monetary cost, and transparency on usage. Finally, we discuss how we as the administrators of on-premise supercomputing systems can provide a better way to encourage users to execute their jobs on the cloud computing resource instead of on the on-premise computing resource under our service policy.

Due to extreme weather, record-breaking heavy rainfalls frequently cause severe flood damages. Thus, there is a strong demand for predicting flood scales to mitigate damages. In this paper, we propose a real-time flood inundation prediction system on a shared HPC system. Although the Rainfall-Runoff Inundation (RRI) model has been developed for predicting large-scale flood inundation, it is necessary to improve the performance for real-time prediction. Since the RRI model is highly memory-bound, we port the RRI simulation code to the latest vector computing system, SX-Aurora TSUBASA (SX-AT), which provides high sustained memory bandwidth. We discuss performance optimization of the RRI code at the node level and MPI parallelization strategies. The RRI code also needs to output intermediate results at a high frequency. Thus, the RRI code is split into file I/O operation and kernel computation, which are assigned to different kinds of processors using the heterogeneity of SX-AT. Furthermore, we discuss a resource demand estimation method to minimize the amount of shared computing resources used for prediction in order to reduce the impact on other users sharing the system. In our evaluation, we demonstrate that SX-AT with only 32 cores can meet the real-time simulation requirement of simulating 7-hour flood inundation for the Tohoku region of Japan within 20 minutes. The evaluation results also demonstrate that the proposed method can adaptively adjust the computing resource amount used for the real-time simulation, and thus reduce the computing resource by 75% in comparison with the worst-case scenario of conservative static resource allocation.

Tropical cyclones are one of the major reasons for catastrophic damage in low-altitude coastal regions. In the last few decades, the world has experienced several devastating damages because of intense cyclones influenced by climate change in the tropical, the sub-tropical and the mid-latitude regions. Therefore, it is necessary to research on the changes in the frequency and intensity of the cyclones influenced by the global warming and to predict the possible damage caused by them using computer simulations. Our aim is to study the characteristics of the high-intensity tropical cyclones using a scientific application, named COAWST, designed to understand the coastal changes caused by the natural processes and to develop a faster model to predict the probable damage with proper warning and with adequate accuracy on the Earth Simulator which is known for one of its kind in the efficient simulation of the natural phenomenon using its high-performance vector processor. In this paper, we have proposed some vectorization strategies on the Earth Simulator to improve the computational performance of COAWST up to 38% to that of its original version for a large simulation. It also aims to showcase the importance of the vectorization technology in order to simulate tropical cyclones related to coastal disasters timely and accurately.

The tsunami disasters that occurred in Indonesia, Chile, and Japan have inflicted serious casualties and damaged social infrastructures. Tsunami forecasting systems are thus urgently required worldwide. We have developed a real-time tsunami inundation forecast system that can complete a tsunami inundation and damage forecast for coastal cities at the level of 10-m grid size in less than 20 min. As the tsunami inundation and damage simulation is a vectorizable memory-intensive program, we incorporate NEC’s vector supercomputer SX-ACE. In this paper, we present an overview of our system. In addition, we describe an implementation of the program on SX-ACE and evaluate its performance of SX-ACE in comparison with the cases using an Intel Xeon-based system and the K computer. Then, we clarify that the fulfillment of a real-time tsunami inundation forecast system requires a system with high-performance cores connected to the memory subsystem at a high memory bandwidth such as SX-ACE.

As the SIMD width of modern microprocessors has been widening for keeping up with the computational demand for HPC systems, recently the vector architecture comes back to spotlight. Besides, a modern vector architecture that has been keeping a large SIMD width and a high B/F ratio has survived and evolved in the HPC community. In this paper, to clarify the potential of the modern vector architecture, we present the performance and power analysis of a modern vector supercomputer SX-ACE using HP-X benchmark programs (HPL, HPCG, and HPGMG). Furthermore, the implementation and optimization of these benchmarks on SX-ACE are discussed. The evaluation results show that SX-ACE achieves the highest efficiencies in the HPGMG and HPCG ranking lists. These facts clearly indicate that the powerful vector processing mechanism with a high B/F ratio is mandatory to achieve a high sustained performance in the future HPC systems.

The cost of maintaining an application code would significantly increase if the application code is branched into multiple versions, each of which is optimized for a different architecture. In this work, default and vector versions of a realworld application code are refactored to be a single version, and the differences between the versions are expressed as user-defined code transformations. As a result, application developers can maintain only the single version, and transform it to its vector version just before the compilation. Although code optimizations for a vector processor are sometimes different from those for other processors, application developers can enjoy the performance of the vector processor without increasing the code complexity. Evaluation results demonstrate that vectorization-aware loop optimization for a vector processor can be expressed as user-defined code transformation rules, and thereby significantly improve the performance of a vector processor without major code modifications.

In recent years, a lot of computer simulation codes have been developed as open-source software. Meanwhile major processors adopt a concept of a vector processing in high performance computing. Hence, the computer simulation codes need to follow a vector processing manner to have a benefit of a computational potential of the vector processing. Our study is evaluation and analysis of performance of various simulation codes developed as open-source software on several vector architectures. In this paper, we evaluate one package of Quantum ESPRESSO as an open-source software code in materials science. Quantum ESPRESSO makes use of several numerical libraries and it is known that parallel parameters called parallelization levels affect the performance in parallel execution. We discuss adjustability of the code to a vector architecture. Moreover, we clarify that the performance of PWscf, which is one of major packages of Quantum ESPRESSO, depends on numerical libraries and parallelization levels of PWscf. For evaluation of performance, we use a vector-parallel supercomputer system named NEC SX-ACE and an Intel Xeon-based cluster system named NEC LX 406Re-2. From this evaluation, we confirm that the code is suitable for vector architectures. Additionally, we clarify the effectiveness of applying optimum numerical libraries to each architecture with appropriate parallel parameters to obtain the high performance.

Achieving a high sustained simulation performance is the most important concern in the HPC community. To this end, many kinds of HPC system architectures have been proposed, and the diversity of the HPC systems grows rapidly. Under this circumstance, a vector-parallel supercomputer SX-ACE has been designed to achieve a high sustained performance of memory-intensive applications by providing a high memory bandwidth commensurate with its high computational capability. This paper examines the potential of the modern vector-parallel supercomputer through the performance evaluation of SX-ACE using practical engineering and scientific applications. To improve the sustained simulation performances of practical applications, SX-ACE adopts an advanced memory subsystem with several new architectural features. This paper discusses how these features, such as MSHR, a large on-chip memory, and novel vector processing mechanisms, are beneficial to achieve a high sustained performance for large-scale engineering and scientific simulations. Evaluation results clearly indicate that the high sustained memory performance per core enables the modern vector supercomputer to achieve outstanding performances that are unreachable by simply increasing the number of fine-grain scalar processor cores. This paper also discusses the performance of the HPCG benchmark to evaluate the potentials of supercomputers with balanced memory and computational performance against heterogeneous and cutting-edge scalar parallel systems.

This paper describes a new-generation vector parallel supercomputer, NEC SX-9 system. The SX-9 processor has an outstanding core to achieve over 100Gflop/s, and a software-controllable on-chip cache to keep the high ratio of the memory bandwidth to the floating-point operation rate. Moreover, its large SMP nodes of 16 vector processors with 1.6Tflop/s performance and 1TB memory are connected with dedicated network switches, which can achieve inter-node communication at 128GB/s per direction. The sustained performance of the SX-9 processor is evaluated using six practical applications in comparison with conventional vector processors and the latest scalar processor such as Nehalem-EP. Based on the results, this paper discusses the performance tuning strategies for new-generation vector systems. An SX-9 system of 16 nodes is also evaluated by using the HPC challenge benchmark suite and a CFD code. Those evaluation results clarify the highest sustained performance and scalability of the SX-9 system.

Vector supercomputers have been encountering the memory wall problem and their memory bandwidth per flop/s rate has decreased. To cover the insufficient memory bandwidth per flop/s rate, an on-chip vector cache has been proposed for the vector processors. Although vector caching is effective to increase the sustained performance to a certain degree, it still needs software and hardware supporting mechanisms to extract its potential. To this end, we propose miss status handling registers (MSHR) and a prefetch mechanism. This paper evaluates the performance of the vector cache with the MSHR and the prefetch mechanism on the vector supercomputer across three leading scientific applications. The MSHR is an effective mechanism for handling subsequent vector loads of the same data, which frequently appear in different schemes. The experimental results indicate that the MSHR can improve the computational performance of scientific applications by 1.45×. Moreover, we examine the performance of the prefetch mechanism on the vector cache. The prefetch mechanism increases the computational performance by 1.6×. Accordingly, the MSHR and the prefetching mechanism are very effective optimization options for vector caching of future vector supercomputers even if the vector supercomputers cannot maintain the current memory bandwidth per flop/s rate.