Table-based models of semiconductor devices are an attractive solution if a physics-based analytical model of the device cannot be found or has insufficient accuracy. Moreover, table-based models offer easy tradeoff between evaluation speed and accuracy. Traditionally, the biggest disadvantage of this class of model has been the inability to take device variability into account. This paper presents a table-based model that can handle process-induced variations of multiple device parameters. The impact of those variations on device operation is modeled analytically using special transformations of the current-voltage and charge-voltage characteristics of the nominal (i.e., variation-free) device. In contrast to multidimensional interpolation between the I-V and Q-V curves of “corner” devices, the proposed approach is much less costly in terms of CPU time, RAM use, and time dedicated to device characterization. The model has been successfully used in statistical simulations of an amplifier and ring oscillator built with VeSFETs-dual-gate junctionless transistors.

The Vertical Slit-based Field-Effect Transistor (VeSFET) is a novel junctionless device with two identical, independently controlled gates. The VeSFET, so far prototyped only as single-device test structures, has been considered in the literature exclusively as a component of digital systems. This paper shows that the device's properties make it attractive also for the analog designer. Some of the VeSFET's analog-design related parameters are compared with those of the MOSFET of the corresponding technology node. Subsequently, a two-stage Miller operational transconductance amplifier (OTA) is proposed that makes use of the VeSFET's two independently-controlled gates to drastically reduce the common-mode gain. An example application of the OTA in a current mirror is also presented.

Circuits with transistors using independently controlled gates have been proposed to reduce the number of transistors and to increase the logic density per area. So far only small building blocks have been presented. This paper investigates for the first time the use of independent double gate transistors in 16 bit ripple carry and parallel prefix adders. New adder circuits and the trade-off between area reduction, delay and power consumption are presented. Area and transistor count reduction by one third can be achieved.

In this paper, we study the circuits built from super-regular, high-density transistor arrays that can be prefabricated and customized using an OPC-free interconnect manufacturing process. The super-regular layout style greatly enhances the chippsilas manufacturability. Unlike other regular fabrics that sacrifice area and performance to improve regularity, the new layout style, combined with a new 3-D geometry transistor, enables to produce circuits with timing and power density comparable to or better than that of conventional CMOS circuits and using less chip area.