Analog-to-information converters (AICs) provide sub-Nyquist sampling rates by signal bandwidth compression, leading to continuous charge accumulation within the circuit. The amplitude of the compressed signal sometimes exceeds the voltage range of the circuits, thereby impacting its precision. The incorporation of voltage boosting and interpolation into flash AIC is suggested to resolve this problem. A voltage boost method with a charge pump generates several reference levels for a comparator. The output of the comparator is subsequently segmented and quantified by hybrid domain quantization, resulting in an interpolated digital sequence. The experimental results demonstrate that the proposed flash AIC is capable of processing a signal with an amplitude range of 1 V while operating on a supply voltage of 0.8 V. It samples the signal at a maximum bandwidth of 25 MHz, at a rate of 12.5 MHz, and achieves 4-bit quantization through the use of a 1-bit comparator. Compared with the current AIC designs, the flash AIC achieves a 2x improvement in the Figure of Merit (FoM), while incurring only a negligible compromise on the reconstructed signal-to-noise ratio (RSNR).

The development of the novel theory of unlimited sampling (US) has enabled analog-to-digital converters (ADCs) to effectively manage input signals with dynamic ranges that far exceed the threshold voltage. However, the existing design of the US asynchronous sigma-delta modulator ADC (US-ASDM-ADC) employs a nonlinear modulo operation within a two-channel architecture to generate the remainder and integer parts, leading to significant amplitude loss due to non-ideal phenomena. To address this issue, we propose a novel single-channel architecture and feedback compensation mechanism for the US-ASDM-ADC. Our approach entails a single-channel folding module to generate the remaining modulo operation while simultaneously generating the integer part of the modulo operation and initiating amplitude correction via a Schmitt trigger-based feedback system. We validate our proposed approach through transistor-level simulations.

The orthogonal matching pursuit (OMP) has been widely explored to realize real-time compressed sensing (CS) reconstruction. The matrix pseudo-inverse of the least squares (LSs) is the most computationally complex operation in the OMP. Among various algorithms to realize this complex operation, the alternative Cholesky decomposition (ACD) algorithm performs the best. However, it typically involves a very long computation time due to its iterative procedure. To accelerate the ACD-OMP algorithm, a novel method called clustered computing look-ahead (CCL) is proposed. Inspired by the famous parallel carry look-ahead adder (CLA), CCL adds a propagation matrix to decouple the data dependency in ACD and then uses a clustering operator to transform the iterative computation of ACD into a pipelined and parallelized computation. This brief also proposes an efficient hardware architecture of the CCL-based ACD-OMP algorithm for CS reconstruction. The proposed algorithm is implemented on field programmable gate array (FPGA). For sparse signals with the same sparsity and length, the proposed implementation is 1.96 times faster than state-of-the-art work.

Along with the rise of edge computing (EC), the cooperation of EC nodes becomes critical, which fuels a growing demand for inter-EC-node (inter-ECN) transfers. Typically, data are transferred in an end-to-end (E2E) manner. However, bulk data, tight transfer deadline and bandwidth fragmentation make such transfers extremely difficult. In this paper, we incorporate multi-path routing and storage on EC nodes into the data transfer, and present an edge-storage-aided multi-path scheduling method (ESMP) for inter-ECN transfers across the EC-enabled optical metro network. ESMP splits the data into chunks and schedules them across link-disjoint routing paths with the help of EC storage. Specifically, within the same deadline for the whole data, a chunk can tolerate longer storing delay and hence can be temporarily stored on an intermediate EC node when its next hop is busy. As a result, a routing path can be split into time-independent sub-paths when the E2E provisioning fails. This improves both the throughput and the flexibility of each transfer. Besides, ESMP can dynamically adapt multi-path routing to balance the completion time and the bandwidth usage based on the current network state. Studies show that compared with the existing scheduling methods, ESMP can accommodate more transfers while reducing the completion time.

In this paper, we propose a novel sensing matrix design for the pulse-width modulation (PWM)-based analog-to-information converter (AIC), which obtains the digital feature of an analog signal rather than its sparse coefficients. The method firstly selects feature subsets by feature selection algorithm of support vector machines (SVMs) and then establishes the relationship between feature subsets and the vector of sensing matrix of PWM-based AIC. Then, a sensing matrix with a higher compression ratio can be obtained. The new optimized sensing matrix is mapped to the reference modulation sequence of the PWM-based AIC’s modulation signal to obtain the PWM-based analog-to-feature converter (AFC). Experimental results show that the PWM-based AFC can reach 99.40% accuracy even when the compression ratio is higher than that of other literature.

Conventional analog-to-information converter (AIC) frameworks employ a discrete-time synthesis sparse model to deal with analog signals, which, however, induces a challenging basis mismatch problem. In this paper, we propose a novel AIC framework, called generalized AIC (G-AIC), to tackle this issue. In the new method, an analysis sparse model is taken, for the first time, as the prior information of analog signals being sampled at sub-Nyquist rate. Through the joint optimization for the discretization operator and its analysis sparse operator, the G-AIC removes the model error between an analog signal and its equivalent discrete samples. To validate the G-AIC framework, we design a single channel G-AIC system based on switched-capacitor (SC) circuits. The circuit design is presented at the theoretical-level, the system-level, and the transistor-level. Numerical simulations demonstrate the G-AIC system can well restore an analog signal from its sub-Nyquist measurements, even though its sparse basis is unknown. Compared with two state-of-the-art AIC systems, the new design can achieve at least 2dB reconstruction gain. In brief, the proposed method provides a promising alternative to exploit analog signals in sub-Nyquist sampling systems.