Vertical integration offers numerous advantages over conventional structures. By stacking multiple-material layers to form double gate transistors and by stacking multiple device layers to form multidevice-layer integration, vertical integration can emerge as the technology of choice for low-power and high-performance integration. In this paper, we demonstrate that the vertical integration can achieve better circuit performance and power dissipation due to improved device characteristics and reduced interconnect complexity and delay. The structures of vertically integrated double gate (DG) silicon-on-insulator (SOI) devices and circuits, and corresponding multidevice-layer (3-D) SOI circuits are presented; a general double-gate SOI model is provided for the study of symmetric and asymmetric SOI CMOS circuits; circuit speed, power dissipation of double-gate dynamic threshold (DGDT) SOI circuits are investigated and compared to single gate (SG) SOI circuits; potential 3-D SOI circuits are laid out. Chip area, layout complexity, process cost, and impact on circuit performance are studied. Results show that DGDT SOI CMOS circuits provide the best power-delay product, which makes them very attractive for low-voltage low-power applications. Multidevice-layer integration achieves performance improvement by shortening the interconnects. Results indicate that up to 40% of interconnect performance improvements can be expected for a 4-device-layer integration.

Article Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors Share on Authors: James Tschanz Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Siva Narendra Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Zhanping Chen Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Shekhar Borkar Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile , Manoj Sachdev Department of ECE, University of Waterloo, Canada Department of ECE, University of Waterloo, CanadaView Profile , Vivek De Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, OR Microprocessor Research Labs, Intel Corporation, 5350 N.E. Elam Young Parkway, Hillsboro, ORView Profile Authors Info & Claims ISLPED '01: Proceedings of the 2001 international symposium on Low power electronics and designAugust 2001 Pages 147–152https://doi.org/10.1145/383082.383121Online:06 August 2001Publication History 39citation804DownloadsMetricsTotal Citations39Total Downloads804Last 12 Months50Last 6 weeks2 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteGet Access

The use of low-threshold devices in low-voltage CMOS circuits leads to an exponential increase in the intrinsic leakage current. This threatens the effectiveness of I/sub DDQ/ testing for such low-voltage circuits because it is difficult to differentiate a defect-free circuit from defective circuits. Recently, several leakage control techniques have been proposed to reduce intrinsic leakage current, which may benefit I/sub DDQ/ testing. In this paper, we investigate the possibilities of applying different leakage control techniques to improve the fault coverage of I/sub DDQ/ testing. Results on a large number of benchmarks indicate that dual-threshold and vector control techniques can be very effective in improving fault coverage for I/sub DDQ/ testing for some circuits.

In this paper, we develop a novel technique based on Markov chains to accurately estimate power sensitivities to primary inputs in CMOS sequential circuits. A key application of power sensitivities is to construct a complicated power surface in the specification-space so as to easily obtain the power dissipation under any distribution of primary inputs, thereby offering an effective power macromodel for high-level power estimation. We demonstrate that such a power surface can be approximated by only a limited number of representative points. This benefit dramatically reduces the CPU and memory requirements. We have verified the feasibility and accuracy of the new technique to estimate power sensitivities on a large number of sequential benchmark circuits. Results on the power dissipation under different distributions of primary inputs demonstrate the efficiency and effectiveness of our power macromodeling technique.

Dual threshold technique has been proposed to reduce leakage power in low v oltage and low p o w er circuits by applying a high threshold voltage to some transistors in non-critical paths, while a low-threshold is used in critical path(s) to maintain the performance.Mixed-Vth (MVT) static CMOS design technique allows dierent thresholds within a logic gate, thereby increasing the number of high threshold transistors compared to the gate-level dual threshold technique.In this paper, a methodology for MVT CMOS circuit design is presented.Dierent MVT CMOS circuit schemes are considered and three algorithms are proposed for the transistorlevel threshold assignment under performance constraints.Results indicate that MVT CMOS design technique can provide about 20% more leakage reduction compared to the corresponding gate-level dual threshold technique.

Reduction in leakage power has become an important concern in low-voltage, low-power, and high-performance applications. In this paper, we use the dual-threshold technique to reduce leakage power by assigning a high-threshold voltage to some transistors in noncritical paths, and using low-threshold transistors in critical path(s). In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high-threshold voltage. A general leakage current model which has been verified by HSPICE simulations is used to estimate leakage power. Results show that the dual-threshold technique is good for leakage power reduction during both standby and active modes. For some ISCAS benchmark circuits, the leakage power can be reduced by more than 80%. The total active power saving can be around 50% and 20% at low- and high-switching activities, respectively.

In this paper, we propose a novel power macromodeling technique for high level power estimation based on power sensitivity. Power sensitivity defines the change in average power due to changes in the input signal specification. The contribution of this work is that we can use only a few points to construct a complicated power surface in the specification-space. With such a power surface, we can easily obtain the power dissipation under any distribution of primary inputs. The advantages of our technique are two-fold. First, the required parameters corresponding to each representative point can be efficiently obtained by only one symbolic power estimation run or by only one Monte Carlo based statistical power estimation process. This stems from the fact that power sensitivity can be obtained as a by-product of probabilistic or statistical power estimation runs. Second, the memory requirements for the macromodel are reduced to O(dn), where n is the number of primary inputs of a circuit and d is the number of representative points (d can be as small as 1 in some cases). Results on a number of benchmark circuits demonstrate the effectiveness of our technique.

Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by IISPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.

In this paper ~vepropose a novel technique based on Markov &tins to accurately estimate polver sensitivities to primary inputs in CLIOS sequential circuits.The po!ver sensitivity y defiues the change in average po~ver dissipation due to changes in the input signal specification.Such sensitivities are estimated a< by-products of the average po~ver estimation, leading to an efficient implementation.A key appUcat ion of po~versensitivities is to construct a polver surface in the specification space so that po~ver dissipation under any distribut ion of primary inputs can easily be obtained, thereby providing an effective po~ver macromodel for high level po~ver estimation.lVe demonstrate that such a po~ver surface can be approximated by ordy a hmited number of representative points.This ;vi~dramaticdy reduce the CPU and memory requirements.Resdts on a large number of benchmark circuits have verified the feasibihty and accuracy of this technique.

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been verified by IISPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50% for some circuits.

Power dissipation in complementary metal-oxide-semiconductor (CMOS) circuits is heavily dependent on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. In this paper, we present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to uncertainties in specification of primary inputs. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using Monte Carlo-based approaches. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.

Power dissipation in CMOS circuits heavily depends on the signal properties of the primary inputs. Due to uncertainties in specification of such properties, the average power should be specified between a maximum and a minimum possible value. Due to the complex nature of the problem, it is practically impossible to use traditional power estimation techniques to determine such bounds. We present a novel approach to accurately estimate the maximum and minimum bounds for average power using a technique which calculates the sensitivities of average power dissipation to primary input signal properties. The sensitivities are calculated using a novel statistical technique and can be obtained as a by-product of average power estimation using a Monte Carlo based approach. The signal properties are specified in terms of signal probability (probability of a signal being logic ONE) and signal activity (probability of signal switching). Results show that the maximum and minimum average power dissipation can vary widely if the primary input probabilities and activities are not specified accurately.