Attaching reconfigurable loop accelerator to a processor is a promising way to improve the performance and efficiency of the system. It's usually to unroll a loop to increase the parallelism of a loop accelerator. While the higher degree a loop is unrolled, the more reconfigurable area is needed. However, an observation is that the utilization of the loop accelerator is relative to the input. Focusing on the area and performance balance, a dynamically adaptive reconfigurable accelerator framework is proposed on CPU/RA architecture in the paper. Firstly, the inputs are classified into certain predefined types. At run-time the input of the application will be monitored and then the accelerator will be reconfigured to accomplish the area-performance dynamic adaption. An accelerator selection model is also presented to choose an accelerator at run-time according to the predefined input types. And a bzip2 case study is presented, the experimental results demonstrated the feasibility of the approach, and shown that up to 93.6% reconfigurable area is saved at a cost of 1.6% performance lost in a best case.

Network on Chip (NoC) has been proposed as a new paradigm for designing System on Chip which supports high degree of scalability and reusability. Mapping an application, which is described by a parameterized task graph, onto NoC is a key research problem in NoC design. In this paper, we first propose an energy-aware cores mapping approach on WK-recursive NoC, and then present a fast clustering-based scheduling algorithm that maps the cores onto WK-recursive NoC architecture under bandwidth constraints to minimize the total communication energy. Experimental results show that the proposed algorithm is able to handle large task graphs and provide near optimal cores mapping in a few seconds on a PC platform.

As the rapidly development of embedded systems, it is a challenge for universities to fill the gap between education and industry. In this paper, we introduce the experiment designed for embedded system curriculum based on embedded IA first, and then adapt the design to the new promising processor-Atom¿ - developed by Intel. At last, we will share our experiences in the experiment teaching of embedded system.

MEMS-based storage device is a new candidate of storage device for pervasive applications which requires large volume of storage. Because of its attractive features such as high-bandwidth, low-power consumption, and low cost compared with hard disk, the storage performance could be significantly improved by adopting MEMS-based storage devices, especially when employing new request scheduling algorithm and data placement A new request scheduling algorithm is explored for MEMS-based storage devices in this paper, which is named parallelism-aware and zone-based shortest positioning time first (PZSPTF). And a new data placement scheme is also introduced, with which the storage area is divided into 2 parts according to 2 file classes, and the files of same class will be stored in the same part. Experiments show that the new PZSPTF algorithm improves the performance of MEMS storage by 7.83% to 18.51% compared with the widely acknowledged request scheduling algorithm FCFS (first-come, first-served).

Nowadays, large storage is becoming an important feature of mobile embedded systems as their media functions are getting increasingly powerful and popular. However, no low power cost memory can provide sufficient capacity at low cost. And much higher power consumption of large capacity storage devices such as Microdrive is hard to be accepted. In this paper, we propose a logical storage layer over hybrid storage device composed of flash memory and Microdrive to provide file systems to embedded systems with minimal impact on battery runtime and power consumption. The result shows that the architecture can provide 32 times as much capacity with 10-15% battery runtime impact.