The autoregressive nature of Large Language Models (LLMs) has enabled remarkable performance in language generation, making them a cornerstone in natural language processing. As context windows lengthen, the per-token key–value (KV) cache grows linearly with sequence length and turns the generation stage into a memory-bound operation. However, existing works focus primarily on an isolated stage of KV cache reduction, and most efforts incur significant hardware overheads. This results in a lack of cross-stage co-optimization and leaves significant reduction potential untapped. To address these challenges, we propose CrossKV, a software-hardware co-design architecture that accelerates LLM inference to fully achieve the potential of KV caching optimization. Motivated by our observation, we identify the three stages in KV caching and present a cross-stage co-optimization algorithm, including: a derivative-enhanced dynamic progressive pruning method, a DCT-driven key-vector low-rank compressing, and a dynamic clustered hybrid run-length encoding to reduce the KV caching while maintaining high accuracy. Then, an efficient architecture featuring cross-stage dynamic co-optimization with negligible hardware overhead is proposed to fully harness the algorithm of CrossKV. Our evaluations of CrossKV over 9 popular LLMs models and various long-context tasks demonstrate an average of$6.03\times $and$4.10\times $improvement for energy efficiency and speedup compared to existing SoTA Accelerators architecture. Compared to the Nvidia A100 GPU, CrossKV achieves an average$23.43\times $energy efficiency and$4.64\times $speedup, respectively.

This article presents a cryogenic fractional-N 4–5.9-GHz cascaded phase-locked loop (PLL) operating down to 4 K for a transmon control system. The main PLL stage employs a supply-boost constant charging current sampling phase detector (SBCC-SPD) to achieve ultralow rms jitter and fractional spur from 300 to 4 K. The first-stage PLL operates in integer-N mode employing an inverter-based sampling PD and a Class-F voltage-controlled oscillator (VCO) to achieve low output phase noise, with a frequency-tuning range of 11.8–15.9 GHz. The second-stage PLL operates in fractional-N mode using double-multimodule divider (MMD) with shared delta-sigma-modulator (DSM) architecture. It incorporates an SBCC-SPD and Class-B VCO, with a frequency-tuning range of 4–5.9 GHz for transmon control application. The reference signal of SBCC-SPD is from the divided signal of the first-stage PLL, which is modulated by the same DSM used in the feedback path of the second-stage PLL to compensate for the quantization error. Fabricated in a 28-nm Bulk CMOS process, the PLL achieves an rms jitter of 58.8 fs at 300 K and 36.9 fs at 4 K, with a fractional spur of −71.8 dBc at 300 K and −69.1 dBc at 4 K. The chip consumes a power consumption of 24.8 mW at 300 K and 14.2 mW at 4K corresponding to a figure of merit (FOM) of −257.1 dB. This chip occupies an area of 0.344 mm2.

With the increasing demand for large-scale model deployment, cloud-based computing remains indispensable. However, energy and bandwidth overheads in edge-to-cloud data transmission pose significant challenges. This work presents a low-power, multimodal SoC that performs on-chip image and audio compression processing, enabling energy-efficient and low-latency cloud interaction for Internet of Things (IoT) applications. The SoC employs a two-level optimization strategy. At the microarchitecture level, a customized 16-bit fixed-length complex instruction set computing (CISC) microprocessor is introduced. Validated against a RISC-V minimal baseline RV32E equipped with equivalent peripheral engines, the proposed core achieves a$5.06\times $reduction in core logic gate count and up to$2.42\times $improvement in energy efficiency under iso-latency conditions. Additionally, a multipower domain strategy is adopted to further optimize energy efficiency, yielding$5.03\times $and$4.13\times $improvements for image and audio modes, respectively. Fabricated in a 65-nm CMOS process, our SoC integrates both image and audio processing, achieving an ultralow power consumption of 54.1–$387.5~\mu $W. It outperforms state-of-the-art dual-modal processors, achieving a$2.84\times $reduction in image-processing core power and a$12.78\times $reduction in audio compression power. Furthermore, our SoC achieves an energy efficiency of 206 pJ/bit of audio task and 15.5 pJ/pixel of image task, which offers a scalable and energy-efficient solution for versatile IoT deployments.

This paper proposes a sample-and-hold amplifier (SHA)-less front-end stage structure suitable for pipeline ADCs in time-interleaving architecture with large interleaving factor. A low resolution SARADC is adopted as the sub-quantizer, and a bridge capacitor is introduced to connect the two capacitor arrays of the MDAC and the sub-ADC. Compared to commonly used pipelined-SAR ADC architectures, the proposed front-end stage structure reduces the reference load on the sub-quantizer during coarse conversion, while preserving the benefits of a shared sampling network in the sampling process. A 14-bit 500-MS/s pipeline ADC channel in an 8-way time-interleaved architecture utilizing the proposed front-end stage structure is designed in 28-nm CMOS process. Simulation results well demonstrate that the proposed front-end stage structure is highly immune to aperture errors, and shows the ADC channel achieves 69.13 dB SNDR and 83.8 dB SFDR at Nyquist frequency. With an estimated power consumption of 40-mW, a Walden FoM of 34.24-fJ/conv.-step is achieved.

This paper presents a PVT-robust, high gain range and high linearity analog baseband (ABB) circuit for wideband communication. The ABB circuit consists of a four-stage programmable gain amplifier (PGA) and an embedded second-order low pass filter (LPF). In order to satisfy the PVT variations, a novel PGA topology based on two-stage miller OTA with self PVT compensation and dynamic pole-capturing technique is proposed. Besides, the ABB circuit uses floating-bulk bias method to achieve high linearity. Fabricated in 28-nm CMOS process, the measurement results show that the ABB circuit can provide a programmable gain range from 0 to 40 dB with 6 dB coarse and 1 dB fine step, while the 3 dB bandwidth greater than 550 MHz. It obtains an OP1dBof 5dBm and OIP3 of 26.1dBm for the maximum gain state. The ABB circuit occupies a core area of 0.23 mm2and consumes a DC power consumption of 15 mW from 0.9-V supply.

This paper presents a high-speed, low-noise and low-offset dynamic latch comparator. In this work, a pair of auxiliary reset transistors is employed to increase the gain of the preamplifier while reducing the reset delay of the latch, which effectively improves the precision and speed of the comparator. The proposed comparator is controlled by two clocks, and the preamplifier is turned on before the regeneration phase to reduce the input-referred noise. In order to reduce power consumption and kickback noise, the preamplifier achieves dynamic operation by controlling a pair of cascode transistors while separating the regeneration node and the input pair. Otherwise, this work optimizes an efficient background calibration circuit to correct the offset. The proposed comparator has been designed and simulated in 12-nm FinFET CMOS technology. Simulation results show a delay of 20 ps at 10 mV input. The proposed comparator also achieves a 0.61 mV input-referred noise and an offset standard deviation of 1.9 mV.

This paper presents an 8-bit 1.6GS/s successive-approximation-register analog-to-digital converter (SAR ADC) with alternate comparators. To enhance dynamic performance and speed, a dither-based background relative offset calibration and a fast SAR logic are proposed. In the background calibration, the least significant bit (LSB) can indicate the polarity of the relative offset between comparators after injecting dither into the input, facilitating calibration without extra phase. The fast SAR logic, which includes a trigger logic and a digital-to-analog converter (DAC) control logic, features a 3-logic-gate delay, resulting in a reduced bit duration. These techniques are validated by a prototype 8-bit SAR ADC in 28 nm CMOS technology, exhibiting the highest speed (1.6 GS/s) and smallest area (0.0008 mm2) among single-channel 8-bit SAR ADC. With a Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) improves from 31.6 dB to 43.6 dB, while the spurious-free dynamic range (SFDR) improves from 38.7 dB to 58.3 dB after offset calibration. It consumes 5.73 mW from 1-V supply, yielding a Walden FoM of 29.0 fJ/conv-step.

This paper presents a continuous-time (CT) Sturdy multistage noise-shaping (SMASH) Delta-sigma Modulator (DSM), proposing a quantization noise extraction scheme without traditional analog delay matching circuits, improving modulator’s robustness and relaxing performance requirement for building blocks. For power-efficiency, the first-stage’s quantizer is designed with a 5-bit Voltage Controlled Oscillator (VCO) based analog-to-digital converter (ADC) and the second-stage’s quantizer is implemented by a 5-bit first-order noise-shaping (NS) successive approximation register (SAR) ADC. A transistor-level prototype is implemented in 40nm CMOS and the simulation results show that the modulator’s SFDR and SNDR is 85.8dB and 70.4dB respectively over a bandwidth (BW) of 20MHz while consuming 7.13mW, leading to an excellent FoM of 164.9dB.

This paper presents a cryogenic qubit controller for scalable superconducting quantum computing. A phase-selection digital power amplifier (DPA) topology is utilized for the XY-driving pulses generation. With a compact digital extensive architecture, the amplitude modulation and qubit phase rotation can be directly implemented at the phase-selection DPA stage for power reduction. A multi-phase envelope-tracking supply unit is also employed to enhance the power efficiency. The controller was designed and simulated in 28nm bulk CMOS technology. The controller can cover a band of 4-6GHz with an output power of at least -8dBm. The simulated SNR/SFDR is better than 55dB/46dB with a phase rotation error of less than 0.7°. The envelope-tracking supply unit can reduce the DPA power consumption by at least 24% compared to a constant power supply. The total power consumption of the controller is 3.64mW.

This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and electrical-magnetic (EM) dual-feedforward techniques are proposed to improve the LNA’s noise performance and reduce the chip area. Design procedures targeting compact chip area, low noise, and high gain are provided. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3 dB bandwidth (BW) from 25.6 to 29.9 GHz, and$-$12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW power consumption. The second LNA employs the current-reuse topology based on the first LNA, which reduces the power consumption to 3.6 mW at the cost of 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65 nm CMOS process. The two LNAs have the same 200$\mu $m$\times$300$\mu $m core chip area. To the best of our knowledge, the first LNA shows the lowest NF and smallest core area at 28 GHz compared with the published CMOS works in a similar frequency range.

This paper describes a balanced frequency shift keying (FSK) modulation, namely quasi-balanced FSK (QB-FSK), for energy-efficient high-data-rate communication. Not suffering from data-pattern dependency, the proposed modulation method enables frequency modulation (FM) over 100 Mb/s by utilizing a wideband phase-locked loop (PLL). The QB-FSK signal is generated with the same baseband clock frequency as the non-return zero (NRZ)-coded binary FSK (BFSK) signal, resulting in improved bandwidth efficiency compared to other balanced FSK signals. For demodulation, the receiver employs a sideband energy detection (SB-ED) method. A FM discriminator converts the QB-FSK signal to an on-off keying (OOK) signal. After that, a band-pass filter (BPF) is used to filter out 1/f noise and dc offset. Based on the proposed QB-FSK modulation and the SB-ED method, a prototype FSK transceiver is implemented in 65-nm CMOS for high-data-rate sub-6-GHz proprietary wireless connectivity. The receiver successfully demodulates data at a rate of 200 Mb/s with a sensitivity of –67 dBm, while the transmitter can achieve a maximum data rate of 400 Mb/s. The 200-Mb/s transceiver achieves an energy efficiency of 0.14 nJ/b.

This paper describes a crystal-less heterodyne phase-tracking receiver (PTRX) architecture that offers a wide tracking range, flexible yet robust loop dynamics, and a 1-bit demodulation output. Unlike the sliding-IF PTRX, a nested integer-N bang-bang phase-locked loop (BBPLL) is implemented within the PTRX to enhance the tracking range by taking the output of an intermediate-frequency (IF) voltage-controlled oscillator (VCO) as an input. The BBPLL also performs phase-to-digital conversion with an oversampled 1-bit digital output. To further improve the demodulation performance, a dual-path injection method with extra control inversion is employed. In the proposed heterodyne PTRX, a phase offset over frequency variation is minimized in the IF mixer. As a result, the mixer-based phase detector in the proposed PTRX has lower gain variation over frequency changes even with a type-I loop, resulting in stable loop dynamics. In this paper, the frequency-tracking and phase-tracking properties of the PTRX are analyzed in view of the jitter transfer and jitter tolerance characteristics of a clock-and-data recovery (CDR) circuit for the first time. The proposed 2.4-GHz PTRX is implemented in 65-nm CMOS, consuming 3.0 mW from a 0.9-V supply. The receiver achieves a sensitivity of –83 dBm at 1 Mb/s.

This paper presents a high linearity front-end circuit for RF sampling ADCs, including an input buffer and a sampling network. The input buffer uses a two-stage NMOS cascode structure and is powered by a separate LDO to support a larger signal swing input with high power supply rejection (PSR) and linearity. We use bootstrap switch with bulk-switching techniques to ensure sampling linearity, while a feed-through compensation technique with self-cancellation of nonlinear junction capacitor is applied to achieve better performance at high-frequency inputs. The above techniques are validated at a 1GS/s ADC in 65nm process, and the simulation results show that the low-frequency PSR of the input buffer reaches over 120dB, and the SNR, SNDR and SFDR of the overall front-end circuit are 78.74dB, 72.37dB and 75.37dB at 2GHz frequency 1.6Vpp input. The −3dB bandwidth of the front-end circuit achieves 4.4GHz.

This paper proposed a wireless 16-channel im-plantable system for long-term neural recording. In order to achieve stable and reliable neural signal acquisition, the im-plantable microsystem consists of an analog front end (AFE), a transmitter (TX), a small battery and a coil for energy harvesting to charge the battery. The AFE integrates 16-channel low-noise amplifiers (LNA), a SAR ADC and a digital interface. The TX integrates a rectifier, a bandgap voltage reference, regulators and a 427 MHz OOK modulated transmitter. The AFE and TX chips were fabricated in 180-nm technology. All the required functional modules are integrated in the chips with off-chip crystal, coil and antenna. The proposed microsystem weighs 2.1 g without a battery, and 3.7 g including the battery. The dimension is$20\times 18\times 7$mm 3. The total current of the system is 1.13 mA, and the battery life is about 50 hours with a capacity of 60 mA$h$. The charging current is 10mA under wireless power transmission.

A Q-learning based current-steering digital to analog converter (DAC) calibration method is proposed in this paper for spurious-free dynamic range (SFDR) improvement. A look-up table (LUT) to control the switching sequence of the DAC elements is achieved by Q-learning for an optimal SFDR. Compared with the fixed element transition strategy proposed by manual derivation, the LUT can be updated by off-line training to deal with diverse and complex non-ideal factors limiting the SFDR of DAC. In this paper, a 2.0-GS/s 12-bit segmented current-steering DAC in 28nm process is simulated and the equivalent model is extracted to verify the effectiveness of the method. Simulation results show that, the SFDR over entire Nyquist bandwidth is larger than 70 dB with about 8 dB improvement using the proposed Q-learning method.

A resource-efficient neural-network-based face detector using 1.5-bit frame-to-frame delta quantization with diagonal spatial feature extraction method is proposed in this paper, which is designed for resource-limited always-on camera sensors. The proposed architecture completes analog-domain frame difference for motion sensing, which triggers digital-domain feature extraction. Based on the sparse and effective features, a lightweight convolutional neural network is devised as a classifier. A self-recorded dataset of 313 videos for humans of different appearances, light intensity and backgrounds is used to validate the performance of the proposed method. Simulation results show that the proposed method achieves 93.6% accuracy using only a$\boldsymbol{50\times 50}$pixel array, which is higher than the prior discontinuous temporal change quantization method. Meanwhile, the conservatively estimated power consumption of the proposed method can be reduced by$\mathbf{14 \times}$compared to the state-of-the-art work.

This article presents a compact 24–30-GHz four-element phased-array transceiver (TRx) front-end (FE) for 5-G communications. A compact T/R switch co-designed with power amplifier’s (PA) output matching network and low-noise amplifier’s (LNA) input matching network is proposed. Leveraging the transformers in the two matching networks, only one extra transistor switch is needed, which greatly reduces the chip area consumption and therefore the insertion loss. A bidirectional phase shifter composed of a two-stage polyphase filter (PPF) and two bidirectional variable-gain amplifiers (BVGA) is shared by both TX and RX. The 24–30-GHz four-element TRx FE is implemented in 65-nm CMOS process. The TX path including the power splitter and T/R switch achieves a measured 11.5-/16.5-dBm OP1dB/PSAT with 12.2%/22.9% PAE$_{\mathrm {1 dB}}$/PAEMAX with 35.1-dB gain. The RX path including power combiner, T/R switch, and off-mode PA achieves a minimum 5.1-dB noise figure (NF) with 25.8-dB gain. The TX and RX paths achieve 5.625° phase resolution with$ < 2^{\circ }$/0.4-dB rms phase/gain error as well as 30.6-dB gain control range with 0.5-dB gain step and$ < 1.5^{\circ }$/0.26-dB rms phase/gain error over 24–30 GHz. Under the 64-QAM fifth-generation (5G) NR FR2 orthogonal frequency division multiplexing (OFDM) measurements, the TX path achieves an average output power of 0 dBm per element (2.1% PAE) with 8.66% EVM, and the RX path achieves an average 4.96% EVM, making the proposed TRx FE suitable for 5G NR FR2 applications. The chip size excluding pads is$4.1\times4.0$mm.

This paper describes an IR-UWB transmitter with an asymmetric pulse which is featured with a steep rising edge and a slow falling edge. The proposed asymmetric pulse not only achieves a better ranging resolution but also reduces the intersymbol interference (ISI) for high data rate communication. For low data rate communication, a frequency hopping (FH) method is applied to the transmitter to enhance the link margin. The proposed UWB transmitter is designed in 65nm CMOS. Compared to the conventional triangle pulse, the ranging variation of the proposed asymmetric pulse is reduced from 120ps to 10ps over process, voltage and temperature (PVT) variations, the transmitter achieves the maximum data rate of 500Mb/s with a pulse energy of 11.5pJ/bit while meeting the UWB spectral mask.

Human bowel sounds (BSs) contain rich information on gastrointestinal health status. Recently, the wearable BS monitoring systems has made it possible to record the human BSs in the long term. However, BSs collected by long-term monitoring devices usually contain various types of noises, which significantly affect the detection accuracy on BS events of interest. To filter out the noises in the long-term BS recordings, a U-Net convolutional neural network (CNN) based BS quality enhancement algorithm is proposed. The algorithm features a frequency-domain BS enhancement using U-Net to efficiently suppress the amplitude spectrum noises of BS segments. Experimental results on our BS dataset show that after enhancing with the proposed algorithm, the average SNR improvement of the sound segments is 28.72dB, which is the best among similar works. Moreover, after the enhancement, the accuracy of BS event detection using a threshold-based approach can reach 98.38%, which proves the effectiveness of the proposed enhancement algorithm. To the best of our knowledge, we are the first to utilize the CNN for BS quality enhancement.

This paper proposed a fully integrated MBAN (2360–2400 MHz) continuous phase modulated transmitter (TX) with tunable less than 0dBm output power for medical band. A duty-cycle tuning strategy was proposed for the power amplifier (PA) featuring adaptive optimized efficiency for different output powers. A fully on-chip transformer-based match network was proposed to suppress the 2nd harmonic using a series$LC$resonator and to suppress the 3rd harmonic by introducing a transformer inter-winding capacitor feedback path. A fractional-N all-digital phase locked loop (ADPLL) with a transformer-based digitally controlled oscillator (DCO) is employed to reduce power consumption as well as improve modulation quality. The transmitter was fabricated in 40-nm CMOS technology, occupying an active area of 0.48mm2. Experimental results show a 26% drain efficiency with −10dBm PA output and 4dB tunable range. A 2mW total power consumption was measured with a TX efficiency of 5% and an energy efficiency of 2nJ/bit. The measured 2nd and 3rd harmonic distortion of the output were −44.3dBm and −57.2dBm, respectively, with on-chip matching network. The measured FSK error of CPM was 2.3% with an M of 2 and 1.57% with an M of 4.

This paper presents an improved correlation-based timing-skew calibration strategy with constant input impedance characteristics. A full sampling rate operating time-interleaved reference ADC (TI-RADC) whose interleaving factor is coprime with TI-ADC is introduced to replace the conventional single-channel reference ADC. This paper theoretically demonstrates that by setting an appropriate time interval between the sampling edge of TI-ADC and TI-RADC and aligning the sampling edge of each channel in TI-ADC with each other but not with the reference ADC, the skew of the TI-RADC would not affect the timing skew calibration of the TI-ADC. A prototype 13-bit 2-GS/s 8-way TI pipelined SAR ADC employing a 1-bit 3-way TI-RADC is fabricated in 28-nm process to verify the presented calibration strategy. Measurement results demonstrate the correctness of the calibration strategy and reveal that compared with using single-channel reference ADC operating at a decimated sampling rate, the spurs resulting from the time-variant input impedance are suppressed more than 20 dB. The prototype ADC achieves an SNDR of 60.36 dB with a near Nyquist rate input when operating at 2-GS/s. The power consumption of the prototype ADCis 252.6 mW (Including the 4.1 mW estimated digital calibration), which translates into a Walden FoM of 148.3-fJ/conversion-step.

This paper presents a four-level pulse amplitude modulation (PAM-4) receiver that incorporates a continuous time linear equalizer, a variable gain amplifier, a phase interpolator-based clock and data recovery, and a 4-tap direct decision feedback equalizer (DFE) for moderate channel loss applications in wireline communication. A dynamic current-mode logic comparator (DCMLC) is proposed and employed in the DFE. The DCMLC, which adopts dynamic logic, breaks the trade-off between the bandwidth and the clock to Q delay in the traditional current-mode logic comparator (CMLC). Compared with the traditional CMLC, the DCMLC reduces the clock to Q delay by 36%, which allows the implementation of a 4-tap direct DFE. Moreover, the first tap feedback signals are directly tapped from the output of the DCMLC, allowing the first tap feedback current to initiate 0.5UI before the decision clock. The PAM-4 receiver prototype is fabricated in a 65nm CMOS process. At a data rate of 56-Gbps, it can compensate for up to 20.17dB loss and achieve a bit error rate$< 1\text{E}$-10 with a power efficiency of 4.75 pJ/bit.

A Ternary neural network (TNN) based patient- specific single lead Electrocardiography (ECG) processor for the early detection of cardiac arrhythmias (CA) is presented. The designed system detects upward/downward turning points in the ECG to detect the slope variation and calculates the fiducial points of the PQRST beats, with high auto-patient adaptability. A 3-layer Feedforward Neural Network with ternary weights is integrated on the sensor to classify eight different types of Shockable CA (SCA) and non-SCA (NSCA) with sensitivity and specificity of 99.1% and 99.8% respectively. The proposed processor is also synthesized using 65nm CMOS technology having an area of 1.08 mm2with an overall power consumption of 2.52 μA, energy efficiency of 72 nJ/detection.

This paper presents a 915MHz band ultra-low-power receiver with high energy efficiency for IoT applications. With the proposed polar receiver topology, the received Star- 16QAM signal is split into an ASK signal and D8PSK signal. A phase-tracking loop working as a phase domain ADC is adopted to demodulate the D8PSK signal, while the ASK signal can be demodulated by using a mixer-based energy detector chain. The receiver was designed and simulated in 65nm CMOS technology. Under 1V supply voltage, the power consumption of 445 μ W and the energy efficiency of 110pJ/bit have been achieved, which is at least 3.5× and 7.1 × better than prior arts, respectively. The simulated sensitivity is -76dBm at a data rate of 4Mbps. The figure of merit (FoM) of the receiver is 176dB.

An analog-intensive voice feature extraction method based on time-domain filtering is proposed in this paper, which solves the computational complexity problem in Mel Frequency Cepstral Coefficient (MFCC) extraction. Compared with MFCCs, the estimated power consumption of the proposed feature extraction is reduced by approximately 4×. Besides, a binarized neural network model called DSXNOR-Net with low parameters is proposed together with the generalized end-to- end (GE2E) loss function for speaker verification. The feature extraction method and DSXNOR-Net are verified by Python. The proposed architecture achieves an optimal recognition accuracy of 98.3% on an English spoken digits corpus for keyword spotting (KWS) and 94.4% on TIMIT corpus for speaker verification (SV). The total estimated power consumption is reduced by approximately 2X and 4X for SV and KWS compared to the state-of-the-art results.

This paper discusses different design aspects of the ΔΣ fractional-N bang-bang PLL (BBPLL) compared with conventional analog or digital fractional-N PLLs performing linear phase detection. Several in-band noise reduction methods without relying on a high-performance digital-to-time converter (DTC) are considered at the architecture-level. It is shown that two-stage topology, single-bit ΔΣ modulation, and phase-domain filtering methods can improve the in-band phase noise, which is different from the conventional PLLs. It is also shown that two-point modulation is superior to one-point modulation regardless of data rate when an overdamped BBPLL is employed for frequency modulation. By integrating those in-band noise reduction methods, we propose a DTC-free, calibration-free ΔΣ BBPLL architecture that achieves the inband noise of about -100dBc/Hz. Behavioral simulation results show that the in-band noise performance can be improved by nearly 40dB without having the DTC.

Stripe extraction is a deciding factor in the multi-line structured light systems. This paper introduces a method to extract the deteriorated stripes in a robust and accurate way. Based on the photoelectron crosstalk phenomenon of image sensors, mathematical expression of the ideal cross-section distribution for the captured stripes is deduced. Then, we establish a probability model for each pixel, with the consideration of how well the local distribution fits the ideal distribution, and how possible it is linked with the previous stripe centers. Therefore, the extraction process is transformed into a local searching scheme with dynamic update. Experimental results show that the robustness of the proposed scheme outperforms other methods. The root mean squared error of the reconstructed point cloud is 0.219mm, which proves the validity of the proposed method.

A 12-bit 2-GS/s pipelined analog-to-digital converter (ADC) front-end stage in 28 nm process is presented. Sample-and-hold amplifier-less (SHA-less) structure is adopted to avoid additional noise, nonlinearity, and power. Aperture error tuning is presented to mitigate the inherited problem of the SHA-less structure. New split closed-loop multiplying digital-to-analog converter (MDAC) structure and 1.2 V dual- input amplifier is used to lower the power and to enhance the speed. Dithering is adopted and comparator threshold voltage dithering is modified for low supply voltage and higher speed. Simulation shows a 66.4 dB signal-to-noise-and-distortion ratio (SNDR) and 76.1 dB spurious-free dynamic range (SFDR) under 1.38 GHz input frequency. The wideband input range and the aperture error tunability are proven by the simulation. The 163.8 dB Schreier figure-of-merit (FoM) and 52.2 fJ/conv.-step Walden FoM is achieved based on an assumed 180 mW total power, of which 90 mW is consumed by the front-end stage.

Forward-looking sonar (FLS) often suffers from complex underwater environments. It is hard to detect small objects from the FLS imagery characterized by low signal-to- noise ratio and low resolution. To highlight the object from severe noise background, we propose an object enhancement method for objects in the regions of interest (ROIs) based on multi-frame image fusion. This method includes two crucial steps: 1) A Fourier-based multi-stage registration algorithm is proposed to solve the problem of a drastic change of object position between frames due to long target distance and rapid change of azimuth angle. 2) A multi-frame fusion algorithm based on self-supervised deep learning is adopted to enhance the ROIs. Experimental results demonstrate that our proposed enhancement method can significantly highlight the objects in the ROIs and has excellent noise suppression in terms of quantitative metrics and visual quality.

The “event-driven” feature of asynchronous circuits enables the circuits to work when and where needed, making it a good alternative to design low-power circuits. However, asynchronous circuits are not widely adopted as a consequence of the lack of support by conventional EDA tools. In this article, we propose a novel design flow to implement the Click-based asynchronous bundled-data circuits efficiently down to mask layout with conventional EDA tools. To ensure timing correctness, we put forward an adaptive delay matching (ADM) method and perform accurate static timing analysis for the circuits. Compared with other asynchronous toolsets, the proposed design flow is more efficient and convenient to implement asynchronous circuits. An asynchronous convolution neural network accelerator is implemented in TSMC 180- and 65-nm CMOS process, respectively, to verify the proposed design flow. The silicon test results show that the asynchronous acceleratorhas 30% less power in the computing array than the synchronous one in the TSMC 65-nm CMOS process, and the energy efficiency of the asynchronous and synchronous accelerators are 1.539 TOPS/W and 1.37 TOPS/W, respectively. The energy efficiency of the asynchronous accelerator in the TSMC 180-nm CMOS process is 133 GOPS/W.

This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-band phase noise over different supply voltages. To mitigate ΔΣ quatization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 mW at 1.2 GHz. The phase noise of-97 dBc/Hz at 1-MHz offset frequency and the reference spur of-76 dBc with the programmable notch filter are achieved. The measured in-band fractional spur levels vary from-37 dBc to-58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems.

This article describes a gain-stabilized integration time generation technique suitable for the pipelined successive approximation register (SAR) analog-to-digital converter (ADC) utilizing an open-loop integrator-based residue amplifier (RA). The gain variation of RA under different process, voltage, and temperature (PVT) conditions is alleviated by adaptively adjusting the length of the generated integration time. A 13-bit 312.5-MS/s two-stage pipelined SAR ADC employing the presented technique is fabricated in a 28-nm process. At a sampling rate of 312.5 MS/s, the prototype ADC achieves a 65.1-dB SNDR and a Walden FoM of 13.95 fJ/conversion-step with an over Nyquist input. Less than 1-dB SNDR variation are obtained for supply voltage varying within ±60 mV and the temperature varying from -40 °C to 120 °C, respectively.

The discrete-time amplifier has the property of sample and hold, thus it is difficult to adopt local feedback method to deal with offset and flicker noise. A calibration-free swap-combine noise cancellation technique is proposed to remove the input-pair-introduced mismatch in discrete-time amplifiers with keeping the same external interface so it can directly replace the original amplifier. The proposed method can eliminate the flicker noise by modifying the noise transfer function, as well as achieve significant offset suppression. Simulation of a prototype shows that it can reduce the offset root mean square from 10mV to 0.25mV. Benefiting from avoiding calibration loops, the proposed method can also deal with input common-mode voltage variation and temperature drift, as well as reducing the calibration area cost and initial delay.

The difference in EEG data among subjects and sessions is an essential factor affecting the accuracy in neural signal analysis. This paper proposed a Tri-FeatureNet, an adversarial learning-based feature extraction algorithm to learn representations invariant to subjects and sessions for sleep staging. The proposed work improves the algorithm's robustness to individual differences. The invariant features are combined with the subject-specified features and the temporal features to further compensate for the loss of sleep information during adversarial training. The proposed model makes use of the temporal information in EEG signals and sleep staging sequences at the same time. This is the first time that adversarial training was proposed to extract the task-related features for different subjects and different sessions in sleep staging. The proposed algorithm was implemented in a portable sleep staging system. Experimental results illustrated an 82.9% ACC in sleep staging task with a single-channel EEG signal.

A competition-cooperation teacher-student model is proposed for knowledge transfer between channels for sleep staging. The teacher model was trained simultaneously with competitor and cooperator student models. One extra “competitor” student model was added to the traditional teacher-student model. The performance of the teacher model can be optimized during the competition with the competitor model. The over-fitting of the student model is greatly reduced in cooperation with the teacher model. A three-step competition-cooperation training process was proposed to optimize the performance of both the teacher model and the student models. The experimental results demonstrate a 2.7% and a 1.6% improvement of the accuracy for the teacher model and the student model, respectively. A state-of-the-art sleep staging accuracy of 83.7% with single-channel input and 85.9% with multi-channel inputs was achieved by the proposed algorithm.

This paper presents a power efficient 12-bit successive aproximation register analog-to-digital converter (SAR ADC) operated at a supply voltage of 0.6V. A binary-scaled redundant technology for SAR ADC is proposed based on split-capacitor DAC architecture. It suppresses the decision error without sacrificing the resolution. In addition, a feedback controlled bias technique is applied to the comparator reducing the power consumption for comparison by 21.6%. The proposed ADC was fabricated in 0.18μm CMOS technology, occupying an core area of 0.07mm2. The measured DNL and INL is +0.46/-0.50 LSB and +0.98/-0.95 LSB, respectively. A SINAD of 68.1dB and SFDR of 83.0dB are achieved, respectively, while operating at a sampling rate of 100kS/s. The power consuming of the proposed ADC is 1.35uW, resulting in an FOM of 6.5fJ/Conversion-step.

Motivated by the ultra-low power design demands of the integrated implantable medical electronics and systems, a switched-capacitor DC-DC converter is presented in this paper. The DC-DC converter is controlled by hysteretic control approach, which has inherently stable and fast loop speed compared with the approach using error amplifier. To achieve higher power efficiency and lower quiscent current, in addition to optimizing the switching frequency and width of the core module of the converter, Low power design methodes are used for the functional module. By operating transistors in the subthreshold region and decreasing operating frequency, the short current and dynamic power can reduce a lot. The converter has designed in 0.18μm standard CMOS technology. It can achieve step down voltage conversion of 1.2V with a ripple voltage of 1.4mV from 2.5V input voltage. A high power efficiency of 88.3% can be achieved at a load current of 3μA. It also produces about 34nA low quiescent current without load, which is suitable for the integrated implantable biomedical electronics.

Impedance matching plays an important role in radio frequency circuits. To achieve dynamic load modulation in back-off operation for power amplifier or address the variation of antenna impedance due to complicated environment, tunable matching networks are demanded. To optimally design the coverage area within the Smith Chart for common ladder networks, analytic calculating procedure and computer optimization method has been proposed. The calculating procedure can be applied to arbitrary ladder networks and the optimization algorithm can acquire the optimal network automatically with appropriate constraints.

This paper describes a low-voltage fractional-N hybrid phase-locked loop (HPLL) architecture that does not require current biasing. A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection. The analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. To mitigate ΔΣ quantization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed bias-free fractional-N HPLL is implemented in 65nm CMOS. At 1.2GHz output, the phase noise of -97dBc/Hz at 1MHz offset frequency and the reference spur of -76dBc with the programmable notch filter are measured. When 14nm FinFET technology is used, simulation results show that a 1.2GHz bias-free PLL can be designed with a 0.4V supply.

This paper presents a fully-integrated 8 MHz relaxation oscillator for ultra-low-power applications. Fabricated in 0.13 μm CMOS process, the oscillator occupies an area of 0.022 mm2. With adaptive reference generation and low-swing oscillation design, the power consumption is 2.8 μW, resulting a figure-of-merit of 0.35 nW/kHz. The adaptive reference feedback compensates the comparator delay and filters out the low-offset frequency part of the noise and temperature variation. To reduce the frequency influence due to current mismatch on the reference voltage and oscillation node, cascode current mirrors are applied. To reduce the influence due to the delay of capacitor reset logic, a pulse-to-edge generation block is used. The measured temperature stability is 1.24% in the temperature range of -20 °C to 60 °C and the measured periodic rms jitter is 180 ps, 0.144 % jitter-per-period on the output.

Human bowel sounds (BSs) deliver much useful information about gastrointestinal health status. In recent years, the utilization of advanced bio-acoustic sensors, such as the wired electronic stethoscopes and the wireless wearable sound recording patches, has enabled researchers to record, store and analyze the BSs in digitized manners, i.e., computerized bowel sound analysis. However, for collected BS recordings, how to effectively pick up the segments that contain BS events while ignoring those segments that only contain background noises remains difficult. Moreover, the BS segment recognition algorithms that are meant to be applied in the wearable healthcare scenes are further required to retain a low computation complexity. In this work, a light weighted BS recognizer based on convolutional neural networks (CNNs) is proposed for wearable systems. Specifically, the proposed recognizer firstly converts each one-dimensional segment into a two-dimensional spectrogram by calculating the Mel-frequency cepstrum coefficients (MFCCs) frame by frame and then passes the spectrogram through a CNN to infer the category of the segment. To validate the CNN-based BS recognizer, a 28 minutes of BS dataset that contains 955 BS-present segments and 725 BS-absent segments are made. Experimental results on the dataset show that the recognizer attains the 91.25% and 90.83% mean accuracies for the `not-across-subjects' and `across-subjects' validation, respectively. Moreover, compared with the state-of-the-art LSTM approach, the CNN-based BS recognizer is light-weighted with only 20.35k parameters, which is a quarter of that of the LSTM. Due to the lower model complexity, the CNN-based BS recognizer has the potential to be integrated into the gateways in a wearable system to secure the function that only the BS-present segments are allowed to be relayed to the remote. User privacy can be better protected in this way.

This article presents a 14-bit 200-Ms/s pipelined analog-to-digital converter (ADC) for wide input frequency range. The ADC adopts a sample-and-hold amplifier-less (SHA-less) 3.5-bit front-end stage. A dedicated path combining architecture is proposed for the flash sub-ADC-based pipeline ADC to reduce the aperture error, and expand the ADC input frequency up to 490 MHz under 200-Ms/s sampling rate. To further improve the accuracy and reduce power, the sampling capacitor splitting and comparator interpolation techniques are used in the first stage. The proposed ADC has been designed and fabricated in a 180-nm CMOS technology with an area of 2.43 mm2including ADC core, the biasing, and the calibration circuit. The measured signal to noise and distortion ratio (SNDR) is 70.6 and 65.6 dB for 30- and 385-MHz inputs, respectively. The SNDR remains 63.1 dB for 490-MHz input. The ADC core consumes 112-mW power under 1.8-V supply. The measured effective resolution bandwidth (ERBW) is about 250 MHz, and the Walden figure of merit (FoM) defined at the ERBW is 116 fJ/conversion-step.

This paper presents an energy-efficient high data rate constant-envelope modulator based on a frequency-domain on-off keying (FOOK) modulation method. The fully-balanced frequency-shift keying (FSK) feature makes it possible for an integer-N PLL to perform modulation with a VCO only (1+-point modulation). By having Gaussian filtering and carrier spreading (CS) techniques, the proposed Gaussian FOOK (G-FOOK) modulation offers a fully-balanced FSK with good bandwidth efficiency and spectrum compliance. A prototype 5GHz G-FOOK modulator is designed with 65nm CMOS process to verify the proposed modulation. The modulator achieves a data rate of 50Mb/s, consuming 6.8mW from a 1V supply. Simulation results show that the proposed modulator can also achieve a data rate as high as 1Gb/s modulation.

Convolutional Neural Network (CNN) is a very popular method in recent times to solve many computer vision tasks. However, CNN is becoming computationally intensive as time is progressing which requires a dedicated hardware for real time implementation. Graphics Processing Unit (GPU) and Field Programmable Gate Array (FPGA) are two hot choices to execute and accelerate the CNN network. FPGA has an advantage over GPU due to its flexible architecture and it can also provide high performance per unit watt of power. These benefits make FPGA a suitable candidate for CNN acceleration. However, optimization is required for FPGA based accelerator design to accommodate more computations. One of the challenges in accelerator design is to perform addition of intermediate results generated in a process of convolution. Therefore, Multi-Operand Adders (MOAs) are necessary in the accelerator design of CNN on FPGA but consume most of the area. Optimization strategy based on WALLACE tree architecture is proposed in this article to replace the typical binary adder tree in CNN accelerator design. Experimental results show an improvement in terms of area optimization and performance in comparison with the previous implementation.

This paper presents an effective way of noise and spur reduction in the design of ΔΣ fractional-N bang-bang phase-locked loops (BBPLLs). An integer-N BBPLL based phase domain low pass filter (PDLPF) significantly suppresses the high frequency quantization noise of the ΔΣ modulator in the feedback path, which mitigates phase folding effects of the bang-bang phase detector (BBPD). A ΔΣ fractional-N BBPLL, combined with the PDLPF for deterministic jitter (DJ) reduction, is implemented in 65nm CMOS. Simulation results show that the proposed architecture achieves an in-band noise reduction of 27dB and a spur reduction of 23dB at 5GHz output with the PDLPF enabled.

The sense and avoid capability enables insects to fly versatilely and robustly in dynamic and complex environment. Their biological principles are so practical and efficient that inspired we human imitating them in our flying machines. In this paper, we studied a novel bio-inspired collision detector and its application on a quadcopter. The detector is inspired from Lobula giant movement detector (LGMD) neurons in the locusts, and modeled into an STM32F407 Microcontroller Unit (MCU). Compared to other collision detecting methods applied on quadcopters, we focused on enhancing the collision accuracy in a bio-inspired way that can considerably increase the computing efficiency during an obstacle detecting task even in complex and dynamic environment. We designed the quadcopter's responding operation to imminent collisions and tested this bio-inspired system in an indoor arena. The observed results from the experiments demonstrated that the LGMD collision detector is feasible to work as a vision module for the quadcopter's collision avoidance task.

A wearable ECG monitoring device with accelerometer aided activity recognition is proposed in this work. A 3-axis accelerometer is integrated in the Band-Aid alike wearable device which will be stuck to the user's chest. The Lead V2 ECG signal and the chest acceleration data are recorded synchronously. An activity recognition algorithm is proposed to identify certain types of daily activities, including coughing, walking, standing, sitting, squatting or lying based on the chest acceleration data. The recognition result can be further used to correlate the recorded ECG signal to the user's activity. Experiments on 13 volunteers with age of 5 to 68 show that the proposed algorithm have an overall accuracy of 96.92%. The recognition result can be further used to correlate the recorded ECG signal to the user's activities.

This paper presents the design of a low-noise chopper amplifier for neural signal acquisition in the presence of the in-band stimulation artifacts that exist in the closed-loop neuromodulation system. In order to avoid saturation due to the artifacts, the gain of the amplifier is designed to be 26dB. A modified positive feedback loop is introduced to boost both inband and DC input impedance. The Gm-C integrator without external capacitors is used in the DC-Servo-Loop (DSL) to filter out the electrode offset. To further enhance the linearity, the voltage divider technique is employed at the input of the Gm-C integrator. The proposed work was fabricated using a 0.18um CMOS process. The amplifier consumes 3.42μW under 1.8V supply voltage, while occupying an area of 0.219mm2. The measured input-referred noise is 1.12μVrms(1 Hz-200 Hz) and 4.65μVrms(200 Hz-5 kHz). A DC input impedance of 90MΩ, a CMRR of 103dB, and a PSRR of 78dB are achieved as well.

The success of the Unicondylar Knee Arthroplasty (UKA) surgery generally depends on whether the implantation of the single compartment knee prosthesis is appropriate. The trajectory of the femoral prosthesis relative to the gasket is an important factor in judging an appropriate implantation. In this paper we propose an UKA trajectory measurement system which includes the pressure sensors array, the data processing part and transceivers. The data is transmitted wirelessly and displayed on the screen in real-time. The algorithm for determining the maximum pressure point and trajectory fitting is put forward, in which a pressure distribution model with distance as the weight is established. According to this model, the number of the sensors used to calculate the maximum pressure is reduced significantly and the initial solution of the maximum point of pressure is obtained. The surrounding pressure sensors are then used to verify and solve the exact solution of the maximum point of pressure with the basic idea of machine learning. Finally, the improved least squares method is used to fit the trajectory of the maximum points of pressure. From the simulation results, we can find that the computational complexity of the algorithm is reduced and the calculation speed is improved compared with that based on finite element analysis or cubic spline interpolation, which meets the real-time requirement. Moreover, the algorithm in this system is easily to be realized in hardware in future work.

A 14-bit 250MS/s low power pipeline analog-to-digital converter (ADC) implemented in a 0.18μιη CMOS process is presented in this paper. A SHA-less 3.5-bit front-end is adopted to achieve low power design. An aperture error eliminating technique and flash ADC optimization design techniques such as capacitor splitting, interpolation, and offset calibration, are both used to achieve wideband input even for the front-end with resolution up to 3.5-bit. The post simulation results show this ADC achieves an SNR of 74.6 dB, an SNDR of 74.4 dB and an SFDR of 87.1 dB with a 70MHz input signal, while maintaining an SNR > 72.5 dB and an SFDR > 77.4 dB up to 900MHz input signals. The ADC consumes 120mW from a 1.8 V supply.

This paper presents a low-power 2-channel 12-bit 2GS/S time-interleaved pipelined-SAR ADC in 28nm CMOS process. The design adopts SHA-less front-end, capacitor sharing between stages, current-reused and ping-pong operated MDAC amplifier, and hybrid reference buffer to reduce power consumption and optimize performance. Pre-layout simulation with noise shows that the proposed ADC achieves SNDR and SFDR of 64.1dB and 69.5dB respectively at Nyquist frequency. The effective resolution bandwidth is extended to 3.2GHz. The ADC consumes only 50mW, in which 30mW is dissipated by the wide-band input buffer. At Nyquist frequency, the proposed ADC achieves a Waiden FOM of 19fJ/conv.-step.

This paper presents a high-frequency pulse stimulation (HFPS) output stage of neuro-stimulator with extended average output current range and high power efficiency. The output stage features two parallel buck-boost converters without any filter capacitor at the output node. Compared with HFPS output stage with only one converter, the proposed circuit doubles the maximum average current by staggering the output of two converters. Compared with traditional voltage mode stimulation (VMS), HFPS improves the power efficiency by discharging the inductor current through the tissue load directly, rather than through a filter capacitor with constant voltage. Besides, the control circuit for the proposed HFPS is much simpler than that of traditional VMS converter, which reduces the current consumption significantly and thus improves the efficiency. Test results confirm that with staggered output of two parallel converters, the maximum average current is doubled. The maximum energy efficiency of the proposed HFPS is 76.4%.

The concept of autonomous cars is driving a boost for car electronics and the size of automotive electronics market is foreseen to double by 2025. How to benefit from this boost is an interesting question. This article presents a case study to test the feasibility of using OpenCL as the programming language and Cots components as the underlying computing platforms for Adas development. For representative Adas applications, a scalable lane detection is developed that can tune the trade-off between detection accuracy and speed. Our OpenCL implementation is tested on 14 video streams from different data-sets with different road scenarios on 5 Cots platforms. We demonstrate that the Cots platforms can provide more than sufficient computing power for the lane detection in the meanwhile our OpenCL implementation can exploit the massive parallelism provided by the Cots platforms.

This paper proposes a static hand gesture recognition method with low computation and memory consumption for wearable applications. The hand contour is chosen as the hand gesture feature and support vector machine is used to classify the feature. A multiscale weighted histogram of contour direction-based direction normalization is proposed to ensure good recognition performance. In order to improve efficiency, the proposed histogram only counts the direction of the contour point to focus on the most significant hand feature in the first-person view of wearable devices. Based on the hand's anatomy, the proposed histogram is weighted by considering each contour point's position and direction jointly using the direction-angle map, to ensure robustness. Experimental results show that the proposed method can give a recognition accuracy of 97.1% with a frame rate of 30 fps on a PC.

A hand segmentation framework is proposed for 3-D hand gesture interaction for wearable devices. In this framework, all the objects in a scene are regarded as directed trees in a forest, and the problem of the hand segmentation can be converted into finding the target tree (called hand tree) in the forest with proper hand properties including color consistency, space consistency, disparity, and hand shape constraints. The forest grows scan-line by scan-line from high reliable regions to low reliable regions. First, the vertices in each tree are generated through boundary detection. To get rid of the interference of skin-colored objects, an under-segment vertex splitting step is added in. Second, a scan-line-based forest growing method is proposed by constructing the maximum spanning forest (MSF) with the edges weighted by the consistencies of color and space. Meanwhile, the high-order history information of the tree construction propagates along each growing tree to the current scan-line to predict the 3-D location of the growing hand tree, so as to achieve semiglobal optimization. At last, the growing hand tree is trimmed and labeled with the disparity and hand shape constraints to correct the misconnection in the MSF. The vertex's disparity is obtained by our multipriority vertex stereo matching algorithm using the 3-D location prediction to overcome the problem of occlusion and high similarity between fingers. Experimental results demonstrate that by using our method, the hand can be well segmented. The score and accuracy of the hand segmentation result is about 96.3% and 92.9%, respectively.

A 4-bit 4Msps successive approximation (SAR) phase-domain analog-to-digital converter (Ph-ADC) for zero intermediate frequency (IF) Bluetooth low energy (BLE) receivers is proposed. With the SAR operation, the Ph-ADC requires only 52 current elements and 1 comparator, in contrast to the conventional design which needs 260 current elements and 8 comparators. Simulation results show that the digital intensive Ph-ADC consumes only 7.9μA current from a 1.8V supply when implemented in a 180nm CMOS process.

An energy-efficiency 16-QAM/MSK transmitter (TX) working at 432 MHz is presented for the short range communications. By adopting the edge-combining power amplifier (ECPA), only an injection-locked ringing oscillator (ILRO) with very low frequency is required, in comparison to the high frequency local oscillator in conventional TX's, which helps to reduce the power consumption of this TX significantly. A new method to control the amplitude of the edge-combined quadrature signals is proposed to generate the 16-quadrature amplitude modulation (16-QAM) and minimum shift keying (MSK) modulations in this work. A finite impulse response (FIR) filter is introduced in the ECPA for side lobe suppression enhancement. Implemented in a 0.18 μm CMOS process, the proposed TX consumes 468 μW when outputting -15 dBm 50 Mbps 16-QAM/MSK signals in simulation. Under 1 V supply, the TX can achieve an energy efficiency of 9.4 pJ/bit at the maximum data rate of 50 Mbps. The phase noise of the RF output in the injection-locked state is -103 dBc/Hz, at 1MHz offset.

Robot-assisted needle insertion technology is now widely used in minimally invasive surgeries. The success of these surgeries highly depends on the accuracy of the position and orientation estimation of the needle tip. In this paper, we proposed an optical tracker based registration method for the marker-robot-needle tip registration in a robot-assisted needle insertion surgery. The method consists of two steps. First, with the guide of the optical tracker, we use the motion vector from the marker's current position to its target point as a feedback control to automatically register the robot-marker and the robot-tracker coordinates respectively. Then, in the procedure of marker-needle tip registration, we use two points on the needle holder to achieve a high accuracy needle orientation registration. We have conducted a series of experiments for the proposed method on a verified platform. Results show that the position estimation error is below 0.5mm and the orientation estimation error is below 0.5 degrees.

This paper proposes a method to build a bare-finger Projector-Camera-Touchpad (PCT) using only one projector and one camera to make any plane become a touchpad. A finger model composed of an elliptic cylinder representing finger pulp, and a quarter ball as the fingertip, is introduced to help fit the finger's pose and size for accurate touch detection and motion tracking. We adopted the color structured light composed of just two kinds of colors, i.e., cyan and magenta, to get depth information of the points on projection pattern for the PCT application. Experiment results show that the accuracy of the touch detection is almost 99% when the finger is under 3mm away from the projection plane and the motion tracking accuracy is under 1 pixel per centimeter, which can satisfy most customers demand. The PCT works just like a real touchpad.

This paper presents an ultra-low voltage and ultra-low power PVT tolerant digital PLL with a semi-digital low dropout regulator (LDO). A low cost integrated temperature compensation circuit (TCC) is proposed and implemented by combining with a proposed ΔΣ LDO to reduce temperature variation of the digitally-controlled relaxation oscillator (DCRXO). A 50-to-145MHz PLL implemented in 65nm CMOS consumes a 77.3μW from a 0.6V supply at 100MHz output and achieves the phase noise of -94.3dBc/Hz at 1MHz offset frequency and the reference spur below -70dBc at 6.25MHz offset frequency. The output frequency variation of open-loop oscillator with the TCC is less than 5% across temperature variation from -20°C to 90°C.

In this paper, we propose an accurate automatic chessboard corner detecting algorithm of sub-pixel precision. The algorithm is based on a novel hyperbolic tangent model. A set of corners are detected initially by Harris' algorithm. Then the hyperbolic tangent model for each corner point is optimized by parameter adjustment. Finally, we use the optimal model to obtain the sub-pixel position of each corner with fake corner elimination. Experiments on three datasets show that the proposed method achieves a detection rate of at least 98% and a reprojection error in camera calibration of at most 0.85 pixels. Our algorithm significantly outperforms the methods in three related works.

This paper proposes a frequency-domain OOK (F-OOK) modulation transmitter with a phase rotator and a 4-stage ring digital/voltage-controlled oscillator (D/VCO) to achieve high energy, bandwidth and area efficiencies. Both frequency deviation and frequency modulation are realized in the phase domain by utilizing the phase rotator. A 9-bit phase rotator covering a phase shifting range of 180° is designed with a phase resolution of 5.625° and phase steps of 32. A hybrid 2.4GHz PLL with a 4-stage ring D/VCO generates orthogonal signals as inputs of the phase rotator. The proposed F-OOK transmitter designed in 65nm CMOS consumes 5.4mW from a 1V supply at the maximum data rate of 10Mb/s, achieving an energy efficiency of 0.54nJ/bit.

A flexible continuous-time ΔΣ modulator that supports both low-pass and complex bandpass (CBP) architectures with the programmable bandwidths of 5 and 10 MHz is presented. By utilizing flexibility into both architectural level and core building blocks, scalable power consumption is obtained for each mode with desired performance. An amplifier topology with active feedforward, antipole splitting, and current reuse techniques is proposed for effective power reduction. A prototyped ΔΣ modulator in a 65-nm CMOS achieves a 65.1-/62.2-dB peak signal-to-noise-plus-distortion ratio (SNDR) with a 5-/10-MHz bandwidth in the LP architecture and a 62.9-/64.1-dB SNDR over a 5-/10-MHz signal band with a tunable center frequency of 4-6 MHz in the CBP architecture, respectively. The figure of merit is 0.21/0.23/0.36/0.24 pJ/conversion step for each mode with a power consumption of 3.1/4.8/4.2/6.3 mW by a 1.2 V supply voltage. The dynamic range is 73/65.8/74.3/74.2 dB. The active area is 0.39 mm2.

Booming wireless connectivity has boosted the interest of source-location in various types of network. The existing performance evaluations of source-location algorithms infrequently focus on the geometry issue, which also has considerable impact on the accuracy of source-location. This paper presents analysis and illustrations of the geometry issue for the time-difference-of-arrival (TDOA) method. Several common source-location algorithms are reviewed, followed by the simulation tests of positioning performance under variants of geometry and different measurement errors. Results indicate that positioning algorithms also work under the examined cases of poor geometry, and an RMSE of below 0.3m can be achieved, which implies that the deviation of time-difference measurement error should be no greater than 33 ps.

A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation is proposed. By utilizing the harmonic rejection (HR) mixer with 12-phase LOs and phase-shift-adding configuration, the IF receiver could eliminate the channel interferences, which is robust to the mismatch. The IF receiver has been implemented in 65nm CMOS, and the simulate d results show that the interference between different channels is below -59dBc, and the IF receiver achieves -12.16dBm-6.52dBm input P1dB, with 21.71mA~23.39mA current consumption from one 1.2 V power supply.

This paper presents a novel autocorrelation-based strategy for timing mismatch calibration in Time-Interleaved ADCs. Different from common technique, the proposed strategy doesn't let autocorrelation between each channel and the reference channel converge to the peak, but to one of the channels with a certain time interval away from the reference channel. It can accelerate convergence. The interval can be selected with much freedom and easily implemented. Representation of sub-ADC output can be only one-bit without a “dead zone”, thus it can further reduce hardware overhead. It's also independent from offset and gain calibration. Using the proposed strategy in a 2-channel 14-bit 500MS/s TIADC, simulation shows a convergence time of 192ms to 0.10/00Tsaccuracy under 212.4MHz input and initial 50/00Tstiming mismatch.

A single-inductor dual-output (SIDO) buck converter with adaptive freewheel current and hybrid mode control is presented in this paper. It operates in pseudo-continuous conduction mode (PCCM) with single freewheel phase to reduce switching loss and minimize cross regulation. Freewheel current adjustment is implemented by detecting and control freewheel time, which can extend the load range and improve efficiency. For unbalanced load, this paper further proposed a hybrid PWM/hysteretic mode control scheme, which enables the two sub-converters to work at their own mode based on the load, independently of each other. The converter was designed with a 0.18μm CMOS process. Simulation results show that the efficiency reaches 87% in PWM mode. At light load, it is still higher than 80%.

This paper presents a method to design a high efficiency energy receiving coil for Micro-Ball endoscopy. The remained space for energy source is extremely small (below 6.6∗6.6∗6.6mm3) in Micro-Ball. Ferrite core is adopted to improve the coupling coefficient. Based on detailed analysis of power loss in the receiving coil, parameters such as number of turns, frequency, types of wires (solid wire or litz wire) was optimized to improve the quality factor of the receiving coil. Ultimately, the coupling coefficient has an improvement of 80%. Experiments shows that the quality factor of the receiving coil (a=b=6.6mm, h=6.6mm) can reach 47 with solid wire and 96 with litz wire at 1.5MHz. Hybrid resonant is proposed to fit in with the load of the Micro-Ball. The AC-AC transmission efficiency of the receiving coil with litz wire is 6.3% in the worst case.

A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta-sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of supporting both narrowband of 5-MHz bandwidth (BW) and wideband of 20-MHz BW. An amplifier topology with active feed-forward and antipole-splitting compensation schemes is proposed. The flexible amplifiers in active-RC integrators and preamplifiers in comparators are implemented with power scaling technique to effectively adjust the power consumption for both BWs. A 1-bit digitally switched current digital-toanalog converter structure with gate-leakage compensation and low-latency dynamic element matching is proposed to cover large current variations and mitigate the gate-leakage issue. Digital I/Q self-calibration algorithm is realized to improve the imagerejection ratio (IRR). Implemented in 65-nm CMOS, the ΔΣ modulator achieves 67.8-/61.4-dB dynamic range, 65.9-/53.7-dB signal-to-noise-plus-distortion ratio, and >60-dB IRR after calibration across 5-/20-MHz BW with center frequencies of 4/12 MHz, respectively. Powered by a 1.2 V supply, the modulator only consumes 4.2/8.1 mW, resulting in measured figure-of-merits of 0.26/0.51 pJ/conversion step.

This paper presents a fast mixed-signal automatic gain control (AGC) method for zero-IF/sliding-IF receivers used in wireless personal and body-area networks (WPAN/BAN). The preamble defined in Bluetooth low energy (BLE)/802.15.4 /802.15.6 specifications are as low as 1 Byte. It is a tough challenge for the zero-IF/sliding-IF receivers to perform AGC training, frequency synchronization and symbol timing estimation. By detecting the RF input of the quadrature mixer, IF input of analog filter and ADC output, the proposed method can achieve a desired IF amplitude within 1 bit when interference signal is small and 3 bits when carrier-to-interference ratio (CIR) is -27dB.

This paper describes an effective way of relaxing the nonlinearity problem of the digitally-controlled oscillator (DCO) in the two-point modulator design. A separate coarse varactor array dedicated for the high-pass modulation significantly simplifies the nonlinearity calibration of the DCO with a few-bit control. In addition, a finite-impulse response (FIR) filter is designed for the multi-bit high-pass modulation path to reduce the quantization noise, while offering a time-interleaving operation to minimize the DCO sensitivity to the coupling during switching time. A two-point modulator based on a semidigital fractional-N phase-locked loop (PLL) is implemented in 0.18μm CMOS. Simulation results show that the proposed modulator can achieve 10Mb/s GFSK/GMSK modulations with the EVM of -37dB.

In order to raise energy efficiency of implantable neural stimulators, an output stage circuit with a self-adaptive stimulating voltage is proposed. The output stage consists of a digital to analog converter (DAC), a single-ended primary inductance converter (SEPIC), a switch array and a current detection module. The SEPIC enables stimulating voltage to vary according to the stimulus current on tissue load or DAC digital input. It improves the output energy efficiency by dynamically cutting down the unnecessary stimulating voltage headroom on the current driver, especially when the stimulus current is small. Simulation showed that the stimulating voltage could change from 1.1V to 18.7V with less than 25mV ripple and the stimulus current could change from 0.7mA to 12.1mA with 0.1mA resolution. The output stage could work smoothly under the voltage supply range between 3.3V and 4.1V. The output efficiency of the proposed work could keep higher than 60% when stimulus current was above 1.4mA and even higher than 70% when stimulus current was above 2.9mA. The output stage is being fabricated on a silicon chip using CSMC 1μm HV technology, occupying 3.46mm×1.94mm.

This paper presents a ΔΣ modulated digital power amplifier (DPA) with a finite-impulse response (FIR) filter for wireless body area network (WBAN) applications. The proposed DPA utilizes a 1-bit second-order ΔΣ modulator to avoid nonlinearity problem of the multi-level quantization and achieve better quantization noise performance than the first-order modulator. The time-interleaving operation inherently provided by the embedded FIR filter mitigates the mismatching effect of PA cells. The proposed architecture not only improves the out-of-band noise performance but also reduces AM-AM and AM-PM distortions. The proposed ΔΣ DPA is implemented in 65nm CMOS. Simulation results show that it can achieve good out-of-band noise performance with the maximum output power of 6dBm and maximum power-added efficiency of 45%.

To improve the accuracy of implant placement in Total Hip Replacement (THR) surgeries, this paper proposes a computer-aided visual system for THR which is composed of a customized acetabular cup, a multi-sensor femoral head trial and a computer for data processing and display. The customized trial is of the same size as the real prosthesis. An image sensor, a gyroscope and an e-compass (including an accelerometer and a magnetometer) are adopted in the femoral head trial. Reference patterns are designed and printed on the internal surface of the cup, whose images are taken by the image sensor for estimation of relative pose and position between the femoral head trial and the acetabulum cup. Two methods of pose estimation are adopted in this system: one based on images and the other based on motion data from gyroscope and e-compass. The efficient perspective-n-point (EPNP) algorithm is used in the image-based pose estimation and achieves a rotation relative error of less than 8% and a translation relative error of less than 10%. The complementary algorithm is adopted in the motion-based pose estimation to smooth the results. Experimental results verified the proposed system.

This paper presents an enhanced voltage reference for Switched-Capacitor ADCs. Charge losing effect is analyzed and quantized. Charge-Compensation-Based (CCB) technique is introduced to reduce the signal-dependent effect. Charge Compensation Unit (CCU) is designed to compensate charge. It features in low overhead on power and chip-size. A proof-of-principle CCB reference design for a 12-bit 500MS/s pipelined ADC is implemented. Simulation results show at least 3dB SNDR and 10dB SFDR improvement achieved, with input sweeping from low frequency to nyquist rate.

This paper presents a combined wireless power transmitting coil designed for endoscopic capsule. In the design, a group of vertically segmented transmitting coils are combined to work. According to the position of the capsule, one, two or three segmented transmitting coils will be selected to work, which makes the capsule closer to the center of the combined transmitting coils. The mechanism ensures high power transfer efficiency and good homogeneity of the energy distribution. This paper also gives the theoretical expression about how to combine the segmented transmitting coils to work together with the highest performances. The experiments show that the minimum and average AC-AC transfer efficiency are 7.53% and 12.7% respectively.

A 0.5-30GHz wideband differential CMOS T/R switch is proposed with low insertion loss (IL), high power handling capacity and high TX-RX isolation. The independent bias technique is proposed to keep the transistors in ideal on/off mode to improve IL and power handling capacity. The leakage cancellation technique is introduced to cancel leakage from TX port to RX port with two match paths. The proposed T/R switch has been implemented in 65nm CMOS, and simulation results show that it achieves 1.2/1.9dB IL and 43/31dBm 1-dB compression point (P1dB) in TX/RX mode and 60dB TX-RX isolation over 0.5-30GHz.

A 4.8-mm20.1-6.0-GHz dual-path software-defined radio transmitter supporting intraband carrier aggregation (CA) in 65-nm CMOS is presented. A simple approach is proposed to support intraband CA signals with only one I-Q baseband path. By utilizing the power-scalable and feedforward compensation techniques, the power of the wideband analog baseband is minimized. The transmitter consists of a high gain-range main path and a low-power subpath to cooperatively cover different standards over 0.1-6.0 GHz with more flexibility. The reconfigurable power amplifier (PA) driver achieves wideband frequency coverage with efficiency-enhanced on-chip transformers and improved switched-capacitor arrays. This transmitter achieves <;-50-dBc image rejection ratio and <;-40-dBc local oscillating signal leakage after the calibration. System verifications have demonstrated -31/- 51-dBc ACLR1/ACLR2 (adjacent channel leakage ratio) at 3-dBm output power for 2.3-GHz LTE20 in the main path and 1.7% error vector magnitude (EVM) at 1.5-dBm output for 1.8-GHz WCDMA in the subpath. Both paths enable SAW-less FDD operations with -153 or -156 dBc/Hz carrier-to-noise ratio at 200-MHz frequency offset. Finally, the dual CA signals with 55-MHz frequency spacing are verified, showing the EVM of 1.2% and 0.8%, respectively, and exhibiting the intraband CA capability.

A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers is presented. The baseband circuit consists of an I/Q calibration circuit, a reconfigurable complex band-pass filter (C-BPF) and an AGC loop. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/ 5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10 MHz and with different center frequencies from 3.996 to 16 MHz. The AGC loop features 5-50 dB gain range and 1 dB step, and digital AGC algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband circuit has been implemented in 180 nm CMOS and consumes 6.5-13 mA variable current thanks to the power scaling technique. The measured image-rejection ratio is 45-55 dB, improved by 22 dB after I/Q calibration.

This paper proposes a new fingertip touch detecting method with high accuracy for the human-computer interaction based on one projector and a single camera. A finger model composed of a quarter-sphere and half a cylinder is introduced, and the relationship between the finger contour and its shadow based on this model is given out. The way to estimate the distance between finger and the projected surface is presented and discussed. Experimental results show that our approach can achieve a precision of about 2mm when the distance from the projected surface to the projector is 50cm and the button size will not influence the precision.

This paper presents a wirelessly monitoring system for Total Hip Replacement (THR) surgery. This system aims to measure and display the attitude and position of femoral head of prosthetic implant during the surgery. The system consists of two parts: the Sensors Array Measuring System (SAMS) and the display part. The SAMS is composed of a sensors array, signal conditioning circuits, a low power Micro Control Unit (MCU), and a low-power transceiver. The SAMS is designed to measure the contact distribution of the sensors array (which is on the surface of the femoral head) between the surface of the femoral head and the acetabulum of the prosthesis. The data is transmitted wirelessly by a low power transceiver. The display part demonstrates the contact distribution and the attitude of the prothesis in-vivo in 3-D images. The two parts of the system communicate with each other on a RF link at the band of 400MHz. The signal conditioning circuits have been designed and fabricated in 0.18μm CMOS process. The tested results show that the resolution of the signal conditioning circuits is 60.1μVpp (1.35g) with ±100mVpp input and the chip can operate under 1.2V to 3.6V voltage supply for single battery application with 116-160μA power current consumption. The system has been validated by experimental results.

A ΔΣ́ all-digital delay-locked loop (ADDLL) is proposed to realize a PVT-insensitive time-to-digital converter (TDC) with enhanced linearity in an all-digital phase-locked loop (ADPLL). With the proposed TDC, poor timing resolution and nonlinearity problems are mitigated, enabling a low cost, low comparison frequency TDC design without using the advanced CMOS technology. A novel digitally-controlled delay line (DCDL) is proposed to ensure monotonous and linear mapping between a digital control word and a total time delay. A phase error compensator (PEC) is employed to calibrate periodic phase error of the proposed TDC. A 2.5GHz ADPLL is designed in 0.18μm CMOS. Simulation results show that the proposed method effectively reduces fractional spurs caused by the TDC.

This paper describes circuit techniques for robust IR-UWB receiver design for high data rate centimeter range communications. For high data rate transmission, multiple frequency bands are utilized to increase transmission power for improved link margin, in the receiver design, a multiband LNA, a fully differential squarer, and a high speed parallel interlacing integrator are developed for high speed data recovery without requiring a high performance analog-to-digital converter. In this work, a 500Mb/s 12.5mW UWB receiver is designed in 65nm CMOS, achieving energy efficiency of 25pJ/b. Simulation results show that narrowband interference from the frequency band of 802.11a wireless standard whose power spectral density is 70dB higher than target sensitivity of -65dBm can be tolerated.

The fetal heart rate is vital for monitoring fetal well-being. Fetal heart rate monitoring based on acoustic techniques is passive and noninvasive. In this work, a fetal heart rate monitoring system based on phonocardiographic method is proposed. A portable low-power stethoscope is customized which meets the need for sensitivity in the monitoring. A noise cancellation method and adaptive matching method are applied to extract the fetal heart rate effectively. Clinical trials are carried out on pregnant women, and the comparison of fetal heart rates given by the proposed system with those given by the Doppler monitor is given to show the accuracy.

In this paper, an intestinal lumen detection method suitable for hardware design is proposed for the locomotive capsule or intelligent Micro-Ball endoscopy. In order to get low complexity as well as relatively high detection precision, a global threshold segmentation algorithm for non-full-shrink lumen and texture based algorithm for full-shrink lumen are proposed. Furthermore, only the red channel of the original Bayer-format image is used in the two algorithms. The computational complexity of the lumen detection method is also given. Experimental results show this method can provide 99.3% precision and 99.0% sensitivity.

This letter proposes an efficient two-step segmentation method for large-scale 3-D point cloud data collected by the mobile laser scanners. First, a new scan-line-based ground segmentation algorithm is designed to filter the points corresponding to the ground with high accuracy. Second, we propose a selfadaptive Euclidean clustering algorithm to further separate the off-ground points corresponding to different objects. Experiments show that our method delivers superior segmentation results on scanned data. In fact, the proposed method can be used in complex scenes including slope and bumpy road at an error rate of 0.674% and a computing throughput of over 20 million points/s.

In this paper, we propose a novel interactive projection system (IPS), which enables bare-finger touch interaction on regular planar surfaces (e.g., walls, tables), with only one standard camera and one projector. The challenge of bare-finger touch detection is recovering the touching information just from the 2-D image captured by the camera. In our method, the graphical user interface (GUI) button is projected on the surface and is distorted by the finger when clicking it, and there is a significant positive correlation between the button's distortion and the finger's height to the surface. Therefore, we propose a novel, fast, and robust algorithm, which takes advantage of the button's distortion to detect the touch action. The proposed touch detection algorithm is performed in three stages: 1) region of interest extraction through a homography mapping, by which the computational complexity of the following processing is reduced; 2) the button's distortion detection using a special edge detection algorithm, which greatly reduces the errors due to the influence of the finger's shadows and edges; and 3) touch action judgment by the button's distortion. Several applications (e.g., virtual keyboard, power point viewing), which use the proposed touch detection method based on the buttons, are shown in this paper. An evaluation is performed on the virtual keyboard and the results demonstrate that the proposed approach can detect bare-finger touch in real time with the missed detection rate of 1.00%, false detection rate of 2.08%, and touch detection rate of 96.92% at the typical projected distance.

Modern graphics processing units (GPUs) are delivering tremendous computing horsepower by running tens of thousands of threads concurrently. The massively parallel execution model has been effective to hide the long latency of off-chip memory accesses in graphics and other general computing applications exhibiting regular memory behaviors. With the fast-growing demand for general purpose computing on GPUs (GPGPU), GPU workloads are becoming highly diversified, and thus requiring a synergistic coordination of both computing and memory resources to unleash the computing power of GPUs. Accordingly, recent graphics processors begin to integrate an on-die level-2 (L2) cache. The huge number of threads on GPUs, however, poses significant challenges to L2 cache design. The experiments on a variety of GPGPU applications reveal that the L2 cache may or may not improve the overall performance depending on the characteristics of applications. In this paper, we propose efficient techniques to improve GPGPU performance by orchestrating both L2 cache and memory in a unified framework. The basic philosophy is to exploit the temporal locality among the massive number of concurrent memory requests and minimize the impact of memory divergence behaviors among simultaneously executed groups of threads. Our major contributions are twofold. First, a priority-based cache management is proposed to maximize the chance of frequently revisited data to be kept in the cache. Second, an effective memory scheduling is introduced to reorder memory requests in the memory controller according to the divergence behavior for reducing average waiting time of warps. Simulation results reveal that our techniques enhance the overall performance by 10% on average for memory intensive benchmarks, whereas the maximum gain can be up to 30%.

In this paper, we model image classification as a Multiple Instance Learning (MIL) problem, by regarding each image as a bag composed of different regions/patches (i.e., instances). Motivated by the fact that a bag is determined by the most positive instance or the least negative instance, which is also called “witness”, we propose a new algorithm to take advantage of witnesses to improve the performance of MIL for image classification task. In the frame of Rate Distortion (RD), we regard MIL as a source coding of each instance to witness or itself, and then the distortion function is measured by the loss of the discriminant model trained on these encoded instances. Hence compared with the existing algorithms, our proposed RDMIL algorithm has the following advantages. First, the probabilistic approach in source coding well illustrates the generative process of witnesses and measures the different importance of instances. Second, the discriminant model trained in a large-margin approach sufficiently considers the diverse influences from the instances, and thus has a strong discriminative ability. The resulted objective function is decomposed into two convex sub-problems, and we especially design a sequential method to effectively optimize the RD sub-problem. Experimental results on two real-world datasets demonstrate the proposed algorithm is effective and promising.

This is the demonstration description of a wireless force measurement system for total knee arhtroplasty (TKA), which will be adopted in the operation to help the surgeons to place the implants quickly and accurately and consequently enhance the success ratio of treatment.

A delay- and phase-locked loop (D/PLL) based clock and data recovery (CDR) system enables an independent bandwidth control for jitter transfer and jitter tolerance but requires careful loop design with PVT-sensitive analog building blocks. In this work, an all-digital DLL and a digitally-controlled type-I boosted-gain fractional-N PLL followed by an injection-locked oscillator (ILO) are designed to realize a semidigital CDR system with enhanced frequency tracking capability and low algorithm jitter generation. The proposed CDR designed in 90nm CMOS consumes 26.4mW from a 1.2V supply and occupies the active area of 1.17mm2.

This paper proposes a new wireless power transfer (WPT) system for the endoscopic capsule. In the system, a group of vertically segmented primary coils around the human body are adopted as the transmitting coils. According to the position of the endoscopic capsule, one of the transmitting coils is intelligently selected to transfer the power with the highest efficiency. This paper also presents a coil selection and control algorithm for the unique WPT system. Compared with the conventional design, the calculated transmission efficiencies of the new solution at the best and worst points of the body are enhanced by 53.5% and 138% respectively. And the average efficiency of the proposed solution is about 3.8%.

A digital background calibration algorithm is proposed to overcome nonlinearity caused by finite opamp gain and capacitor mismatch in pipelined analog-to-digital converter (ADC). The scheme, code frequency statistics (CFS), does not modify the classic pipelined stage, needs none of extra testing signals, and reduces the linearity requirement of the analog circuit. CFS is suitable for generic input and the cost of hardware is low. An experimental 14-bit pipelined ADC is fabricated to verify CFS. At 15MS/s, the measurement results show that INL errors drop from 90LSB to 0.8 LSB, SNDR grows from 38.6 dB to 66.7 dB, THD drops from -37.3dB to -82.8dB, and SFDR grows from 41.6 dBc to 86.1 dBc. The linearity of the pipelined ADC is improved significantly.

This paper firstly proposes a new algorithm for finger touch detection based on front-projected vision-based table system. The algorithm, taking advantage of shadow information, can locate possible finger touch with low complexity. An adaptive structured light method is introduced to improve the precision of touch detection effectively. Secondly, we present a new prototype system architecture and corresponding hardware design for portable bare-hand human computer interaction (HCI). Experimental results show that the accuracy of touch detection of single finger and multi-finger is 98.3% and 92.6% respectively.

The presented SoC is an 8-bit MCU based processor with 32-bit encryption algorithm acceleration and special security mechanism dedicated to mobile one-time password (MOTP) applications. The encryption algorithm accelerator can perform several 32-bit key operations for hash function computation, with each in one clock cycle. The SoC also features protection mechanisms which can prevent attackers from stealing the algorithm program code or the secret key, or utilizing under-voltage attacks. The SoC chip, fabricated in 0.25 μm CMOS process, has more than 50% efficiency improvement on hash function computation if compared with those 8-bit general-purpose MCUs and consumes less than 7.2 μA current in average for typical MOTP applications.

This paper presents a 65nm multi-mode complex band-pass filter (C-BPF) used in low-IF GNSS receivers. It supports the bandwidth of 4MHz, 10MHz and 18MHz, and can be centered at 4.2MHz, 6.1MHz, 12.3MHz and 28MHz. The OTAs served in the filter are realized in arrays which makes the power consumption scalable among different operation modes. In addition, assistant transconductors (assistant-gm) are adopted to compensate the outputs of each OTA stage, which in turn saves at maximum 9mA DC current for the whole filter. In order to achieve higher than 30dB image rejection ratio (IRR), another group of assistant-gms are introduced to the input stage for I/Q mismatch calibration, which is able to regulate a maximum ±3dB amplitude imbalance and ±5° phase imbalance. The filter consumes less than 10mA in the 28MHz-IF, 18MHz-bandwidth mode, and achieves >31dB IRR with the maximum I/Q amplitude and phase mismatch.

This paper proposes a merged first and second stage for pipelined ADC. It merges the first MDAC and second MDAC by using opamp and capacitor sharing technique to reduce power. For low supply advanced CMOS technology, the range-scaling technique is used to reduce output range in this stage, so the single-stage opamp can be used with low supply voltage to reduce power furthermore. The SHA-less technique is also used for the reduction of power and noise. The proposed stage relaxes the requirement for the gain of opamp by about 6dB comparing to the conventional one. For verification, a 14bit, 200MS/s pipelined ADC is designed in a 130nm CMOS process. The simulation results show 73.4 dB SNDR with noise and 88.8dBc SFDR at 95 MHz input frequency. The pipelined core power consumption is about 42mW at 1.2V supply, and the whole pipelined ADC has an energy efficiency of 178 fJ/conversion-step.

A half-rate clock and data recovery (CDR) circuit for 60GHz communication with 20Gbps QPSK modulation in 65nm CMOS is presented. A hybrid DC-offset cancellation loop (DCOC) is proposed to calibrate the input offset. A duty cycle distortion (DCD) cleaning up circuit is adopted to minimize the negative impact on the half rate sampling in the CML-CMOS conversion, and a quadrature clock calibration (QCC) is utilized to correct the input clock I/Q phase mismatch. The CDR is based on phase interpolator (PI) and uses the quadrature clocks from the divider of the main PLL. The whole CDR consumes less than 16mW with 1V power supply and achieves less than 1mV DC-offset, 0.2% DCD and less than 1° residual I/Q phase mismatch after calibration.

This paper presents a novel DC offset calibration method for the zero-IF (intermediate frequency) receiver that removes the PGA-gain-correlated offset residue. The conventional calibration method is usually based on the classic input/output referred offset model, in which the receiver IF programmable gain amplifiers (PGAs) have offset sources that varies a lot with different gain settings. Consequently, the conventional calibration method needs to generate the calibration code at each gain step and requires a huge look up table (LUT) to store the calibration values. This paper presents a new DC offset model which is gain non-correlated, by analyzing two types of commonly-used PGA. Based on the new model, a LUT-free single-step DC offset calibration method in together with the implementation circuit is designed. The proposed method has been verified on a practical zero-IF receiver circuit in a standard 0.18 μm CMOS technology through the Monte Carlo (MC) simulation. The simulation results show that the receiver IF output offset residue after calibration using the proposed method is reduced to below 12 mV, which is comparable to the LUT-based conventional calibration.

This paper presents a pulse-shaped power amplifier (PSPA) design for delay line based IR-UWB transmitters. By utilizing an array of CMOS transmission gates as a dynamic bias scheme, the switched PA generates desired output pulse with negligible static current. The PSPA designed in 65nm CMOS generates UWB pulses with a -10dB bandwidth of 2.7GHz and a center frequency of 5GHz and achieves reconfigurable pulse shaping with high power efficiency. Simulation results show that the energy consumption of the PA is 3pJ/pulse with a typical current efficiency of 90% at a data rate of 200Mbps.

A chipset, including one master chip and six same slave chips, is designed and implemented for the endoscopic Micro-Ball, which has six cameras to minimize the blind area while examining the human gastrointestinal (GI) tract. For lowering power consumption, a multi-level clock management for the whole chipset is implemented. A power and area efficient 4 × 4 JPEG image compressor with high image quality is integrated into the slave chip to reduce energy consumption and save FLASH memory space. The master chip and slave chip have been fabricated in 0.18 μm CMOS technology. The experimental results show that the designed chipset for Micro-Ball can support different image frame rates: from 1fps to 6fps with 480×480 image resolution. The power consumption of the chipset is 1.6mW@2fps. The power consumption of the Micro-Ball is estimated about 6mW@2fps. It can work for more than 15 hours, powered by a 1.55V@60mAh battery.

In this paper, a 10Gbps PI-based CDR circuit is presented in 65nm CMOS technology. The circuit is composed of a phase selector, a phase interpolator, a sample unit, a synchronize unit, a phase detector, and CDR logic. Half-rate clock is adopted to lessen the problems caused by high speed clocks and reduce power. The simulated worst phase step of phase interpolator is 26.7% larger than the average phase error. The power consumption is 15mW for 1V supply.

This paper describes the design of a low-jitter source-synchronous link transmitter macro for data rates of 9.6 Gb/s. The transmitter macro consists of 5 data channels plus 1 forwarded-clock channel. A low jitter PLL with bandwidth linearization is employed to achieve 0.66ps rms jitter. The power supply induced jitter is minimized by employing a hybrid clock distribution network which is proposed for both jitter and power consideration. To minimize the influence of PVT variation, Successive Approximation Register (SAR) sub block is implemented to accurately set the on chip impedance and the signal amplitude. A CML driver with 4 tap feed forward equalizer is implemented to compensate the channel loss. The transmitter is implemented in 65nm CMOS technology, the active chip area is 3.12 mm2.

A wireless force measurement system is presented in this paper. The system, which is used during the operation of Total Knee Arthroplasty(TKA), is designed to assist surgeons to determine the proper position of the knee implants and consequently enhance the success ratio of the treatment. It consists of three parts: a device to measure and transmit force data, a receiver and a terminal to display the force data in real time. The transmitter communicates with the receiver by 2.4GHz Radio Frequency (RF) signal. The system consumes no more than 17mA current with 3V voltage supply typically. So it can work with a button battery cell. Experimental results show that the performance of the system meets the requirements.

This paper proposes a theoretic error analysis framework as well as corresponding calibration methods for a mobile 3D data acquisition system equipped with LiDAR and GPS/IMU. Our framework considers inherent errors of variable sensors, installation errors, and time synchronization errors among different sensors. Our framework is enhanced by an empirical error analysis method based on a triangulated irregular network structure. Experimental results prove that the proposed error analysis methodology can provide accurate and efficient evaluation for mobile 3D data acquisition systems.

This paper presents a 12-bit 270MS/s pipelined analog-to-digital converter (ADC) without employing a front-end sample-and-hold amplifier. A novel strategy is established to diminish the aperture error while maintaining both the original tracking time and amplifying time of multiplying digital-to-analog converter (MDAC). It matches the signal paths between comparators and MDAC in the first stage by using proper timing sequence and high-speed dynamic comparators. The measurement results show 63.7dB SNR and 76.1dBc SFDR at 120.1MHz input frequency while the chip's total power dissipation is 250mW (excluding LVDS drivers) at 1.2V supply. The ADC core occupies 1.7mm2and is implemented in a 130nm CMOS process.

A low-cost low-power baseband processor for passive UHF RFID Tag based on EPC C1G2 protocol is presented in this paper. In order to minimize the power consumption, a novel digital baseband architecture is proposed and a series of low-power design approaches are adopted, including asynchronous design, clock-gating, low operating frequency, reuse of registers, etc. The baseband processor supports eleven mandatory commands and one optional command (Access) and the C1G2 protocol is completely fulfilled. The whole Tag (including a 1K EEPROM, RF/Analog frontend and the low-power baseband processor) is fabricated in 0.18μm CMOS technology. Real measurements on the final chip indicate that the processor consumes less than 2.7μW at 1V supply voltage and occupies an area of 0.11 mm2.

A multi-mode reconfigurable wideband continuous-time lowpass/quadrature bandpass sigma-delta (CT LP/QBP ΣΔ) modulator employing power scaling technique (PST) for LTE-advanced/industry-specialized zero/low-IF receivers is presented. The proposed modulator consists of a loop filter with active-RC integrator configured as 3rd-order lowpass or 2nd-order complex bandpass architecture and 4-bit internal quantizer operating at 80MHz, 160MHz and 320MHz, respectively. A programmable differential current-steering DAC unit is adopted for high linearity. In LP mode, the excess loop delay is set to half the sampling period of the quantizer and an additional feedback DAC is used to maintain stability, which is not used in QBP mode. The modulator employs flexible high gain and high bandwidth amplifiers with PST to optimize power consumption among various modes. Implemented in 65nm CMOS, the modulator achieves 84.8/85.8/84.5dB SNDR, 94.9/94.1/94.6dB SFDR over 2.5/5/10-MHz signal bands in LP modes and 83.8/ 84.6dB SNDR, 94.3/96dB SFDR across 2.5/5-MHz bandwidth with programmable center frequencies of 2/4-MHz in QBP modes, respectively. Powered by a 1.2-V supply, the modulator consumes 1.8 to 4.2mW, which results in simulated FOMs of 15.5 to 27.8fJ/conversion.

This paper presents a power detection based I/Q imbalance self-calibration technique to compensate signal path gain and phase mismatch in a reconfigurable low-IF receiver. The calibration can be carried out at startup to improve the image rejection ratio (IRR) of the IF complex-bandpass filter, and then configuration words are saved. The system employs an analog I/Q calibration module to adjust signal path gain and phase mismatch, a power detector to measure I/Q imbalances, digital circuits to implement the calibration algorithm, and a digital AGC to adjust IF signals within a predetermined level. The self-calibration system is implemented as a part of a multi-mode GNSS (Global Navigation Satellite Systems) receiver. Only one 2-bit ADC in I (or Q) path is needed to sample the analog IF signal. Measurement results show that the calibrated IRR achieves an average of 50dB in different operation modes which gets a 10~20dB improvement. The low-IF GNSS receiver is fabricated in 65nm CMOS process, and the digital part of the self-calibration system is implemented in a FPGA.

This paper presents a single loop 3rdorder 5-bit audio ΣΔ modulator with feed forward path. Feed forward technology relaxes the amplifier design requirement by reducing output swing of the integrators. Chopper stabilization technology is employed to mitigate the flicker noise introduced by 1stintegrator. A kind of asynchronous successive approximation (SAR) quantizer without extra fast clock replaces the traditional flash quantizer. Two voltage reference buffers are integrated on this chip as the input stages of Vrefpand VCMOto simplify off-chip circuits. Simulation results show that the modulator achieves 120dB SNDR under 5 kHz input signal within 20Hz~24kHz bandwidth. The modulator alone consumes only 20mW and the overall power consumption is less than 60mW from 3.3V supply. The active core area is 2.3×1 mm2fabricated in 0.18μm standard CMOS.

A low-power CMOS capacitance-to-digital converter for capacitive sensors array is presented. It consists of a 16-channel MUX, a front-end with wide dynamic range for capacitance-voltage conversion and a novel voltage-pulses convertor. This novel circuit charges the measured capacitor indirectly and converts it into a proportional voltage, and then produces a 16-bits pulses-formed single-line output with multi-steps quantization method. The circuit can operate under 1.2V to 3.6V voltage supply for single battery application. The maximum input is 350pF with 0.75ms/ch update rate and 90μA power consumption when the operating clock is 100KHz. The chip has been design and fabricated in 0.18-μm 1P6M CMOS process with active area of 640×630μm2.

This paper describes a ΔΣ modulation based ranging method for the IR-UWB radar system. To relax the phase resolution requirement of the delay line in the receiver, two coarse timing boundaries of the delay line are used to form a bilevel quantizer which can be the part of a 1-bit ΔΣ oversampling TDC. Also, a digital phase rotator circuit is designed to provide an unlimited phase capture range. Simulation results show that the proposed ΔΣ IR-UWB radar can achieve sub-mm ranging resolution with good matching assumed.

Attitude sensing system is indispensable for wireless Micro-Ball endoscopy to capture the full-view images of gastrointestinal (GI) tract. This paper proposes a novel attitude sensing system design with small size and low power for this application, which is based on MEMS 3-axis accelerometer and magnetometer. To reduce the error caused by tilt angles, a compensatory algorithm is introduced in this design. The experimental results show that the attitude sensing system could measure attitude in real time with high enough accuracy meeting the requirement of the wireless Micro-Ball endoscopy application. The power consumption of the attitude sensing system is about 3mW. The error of pitch is less than 3°, roll is less than 3.1°, and yaw is less than 6°.

The wireless endoscopic Micro-Ball is used to capture images of gastrointestinal (GI) tracts and save them into Flash memories. The batteries will be exhausted after the Micro-Ball is excreted from human body. So a new wireless power transmission (WPT) solution is proposed to deliver energy from an image reader to the Micro-Ball to fetch the stored images. In this solution, considering that the posture of the Micro-Ball is uncertain when it is placed into the image reader and the volume of the Micro-Ball is too small to contain multiple receiving coils, we employ multiple emitting coils in the image reader and one single receiving coil inside the Micro-Ball. Additionally, an adaptive control mechanism is proposed to select the optimum emitting coil with the highest power efficiency to transmit wireless power to the Micro-Ball placed inside the image reader. As a result, the Micro-Ball can work well in the image reader under all postures with highest power efficiency. The experimental results prove that the power delivering efficiency is in the range of 32% to 36%.

In this paper a 1V 15-bit ΔΣ ADC for audio application is presented. Second order modulator with feed- forward path is adopted in order to reduce the swing of each integrator. Non-linear gain effect is mitigated. Single stage amplifier with high power efficiency is employed to save power. Decimation filter is implemented with seven-stage cascade sub- filters. Timing multiplexing and resource reuse methodology are employed for low hardware cost. The ADC is programmed to adapt 4K 8K 16K applications. Over 90dB SNDR performance can be achieved under various bandwidths while the total power dissipation is 360μW. The modulator occupies 0.3mm2and decimation filter occupies 0.2mm2.

This paper firstly presents a CMOS voltage-controlled oscillator (VCO) which enables octa-phase triangular waveform generation. By utilizing a cascaded relaxation oscillator core followed by a pseudo injection-locked oscillator circuit, an octa-phase differential VCO with triangular waveform outputs is realized. Simulation results show that the proposed fully differential multi-phase VCO can achieve broad tuning range with programmable timing capacitors, offering <;1% phase mismatch.

A 0.13 um CMOS 1.5-to-2.15 GHz low power transmitter front-end with direct quadrature voltage modulation for SDR applications is presented. The SDR transmitter front-end consists of PGA, passive RC filter, direct quadrature voltage modulator, 25%-duty-cycle LO generator and programmable PA-Driver with reconfigurable operation frequency bands. An on-chip transformer with switched- capacitor array provides the wide-band reconfigurable frequency band covering and differential-to-single-ended conversion. The passive voltage mixer with 25%-duty-cycle LO implements the frequency up-conversion with low noise and low conversion loss. The SDR transmitter front-end has been implemented in 0.13 um CMOS, the measured results show that this front-end could provide 22 dB gain with a step of 2dB and output higher than OdBm power across 1.5-to-2.15 GHz frequency range with a maximum power consumption of 42 mW. The die area is 1.6 mm* 1.2 mm.

Nowadays the interpretation of the images acquired by wireless endoscopy system is a tedious job for doctors. A viable solution is to construct a map, which is a 2D representation of gastrointestinal (GI) tract, based on image registration to reduce the redundancy of images and improve the understandability of them. Nevertheless, the limited field of view makes it difficult for traditional wireless capsule endoscopy system to capture sufficient image information for a complete GI map. The work reported in this paper addresses the problem of the 2D representation of GI tract based on a new wireless Micro Ball endoscopy system with multiple image sensors. This paper analyses the characteristics of images captured by Micro-Ball endoscopy system and proposes a determination method for registration of wireless endoscopic images based on phase correlation method (PCM). The performance of PCM and the proposed determination method is verified with experiments.

A nanopower subthreshold bandgap reference with 30ppm/°C from -30°C to 150°C has been implemented in 0.18μm CMOS. This design is based on weighted ΔVGSand is free of resistors. The major advantage of this design is that with nanopower consumption, the temperature range is extremely wide. To achieve high performance of subthreshold bandgap operating in high temperature (above 80°C), a leakage current elimination technique which enables subthreshold bandgap operate properly until 150°C was proposed. Such modification does not require additional die area and power consumption. This topology can also generate multiple reference voltages whose values are integer times of the minimum reference voltage. The line regulation of the reference voltage is 0.677mV/V when the supply voltage is increased from 1 V to 2.5 V. The core circuit consumes 46nW at IV at room temperature. The active area occupies 0.0036mm2.

A wide-tuning low-cost PLL architecture with negligible loop filter area is presented. To overcome the static phase error or reference spur problem of the conventional type-I PLL over broad frequency tuning range, a Δ-Σ DAC based real- time frequency acquisition aid method is employed in the PLL voltage domain. Different from other Δ-Σ based frequency acquisition methods mainly used for the type-II all-digital PLL (ADPLL), the proposed method provides inherent quantization noise reduction by the PLL loop filter. Simulation results verify that significant reference spur reduction as well as Δ-Σ noise reduction can be achieved with the proposed architecture.

This paper describes a practical settling time analysis of the charge-pump phase-locked loop (PLL) by considering nonlinear circuit effects on transient settling behavior; a PLL slew rate, a PFD reset delay, and a loop filter charge sharing. A transient analysis including those parameters with a refined lock-in range is given, showing that the overall settling time can be significantly affected by the nonlinear factors even with the same PLL bandwidth. Behavioral simulation results verify that the proposed analysis predicts the transient settling time more accurately than existing methods.

This paper presents a novel ASK demodulator for passive UHF RFID (radio frequency identification) tag, which can detect minimum 10% modulation index over a RF power range of 30 dB. Compared with conventional nonlinear voltage and linear current demodulations, the detection sensitivity over a wider range is increased by adopting an innovative divisional linear voltage demodulation with ultra low power consumption. The demodulator is implemented in UMC 0.18 mum mixed-mode CMOS technology. The power consumption is 3.95 muW and it can be reduced to 3.08 muW when the modulation index is large.

This paper describes a method to control the zeroes in the frequency response of hybrid finite impulse response (FIR) filter in ΣΔ fractional-N PLL for quantization noise reduction. By adjusting the current allocation in different branches of the charge pump, transfer function of the FIR filter can be customized to meet various system requirements. Simulation results shows that the proposed method effectively adds flexibility to the hybrid FIR noise filtering technique while it also helps to reduce the hardware complexity.

This paper presents an energy-efficient implementation of a real-time on-demand MAC protocol for medical wireless body sensor network (WBSN). Medical WBSN is focused on pervasive healthcare and medical applications, such as monitoring vital signs, making basic drug delivery, etc. The sensor nodes in the heterogeneous WBSN generally require different data rates, due to their differing functions. Additionally, because of the strict resource constraints, the sensor nodes must be ultra-low-power. Thirdly, low-rate treatment-function nodes must also ldquowork-on-demandrdquo to prove proper activities in the slave nodes such as stimulus and drug delivery. These three requirements cannot currently be satisfied simultaneously in commonly-used single channel implementations because the channel monitoring consumes too much power for long-term use. In the proposed implementation, a secondary channel is introduced in, which is used for channel listening only. Benefiting from the secondary channel, the node can achieve both real-time ldquowork-on-demandrdquo and zero idle power, by means of recovering energy from the ldquodemand tokenrdquo. An elaborated energy-harvesting RF module achieves monitoring the secondary channel. The prototype system of sensor nodes is expected for the zero-idle-power and the response time of less than 2 ms.

A robust passive UHF RFID backscatter system enhanced with spread spectrum technique is presented in this paper. Due to the weak signal energy of the backscatter chain, traditional RFID backscatter communication is easily affected by the noises, interferences, and interceptions from the environment. To solve the problem, spread spectrum technique is introduced into the backscatter link of RFID system. Simulated results show that this approach largely reduces the bit error rate and improves the system's reliability and security. For hardware realization, spectrum spreading operation is implemented in a RFID tag baseband processor, which is finally applied into a complete RFID tag and fabricated using 0.18 um 1P6M CMOS technology. Furthermore, de-spreading operation including the PN acquisition is integrated into a FPGA implementation of RFID reader. Thus, a complete robust RFID backscatter system enhanced with spread spectrum technique is constructed.

Techniques are proposed to enhance the bandwidth of ultra-wideband (UWB) CMOS low-noise amplifiers (LNA). By using multiple-input-branch technique and resistive shunt-feedback technique, LNA could achieve ultra-wideband input impedance matching with small noise figure degradation. The gain bandwidth is enhanced by an L type inter-stage matching network between the input transistors and the cascode transistor which could enhance both the gain and the gain bandwidth. The gain bandwidth could be further enhanced by the resistors inserted between the bulks and the sources of the input transistors since the resistors could reduce the effects of the drain-bulk capacitance of the input transistors. The techniques proposed offer the advantages of ultra-wideband bandwidth, simple circuit topology, and small chip area. The proofs of techniques are demonstrated by designing the UWB LNA in UMC 0.18um CMOS.

In this paper, an improved method of power control is introduced to widen the range of output power with high efficiency. Two CMOS class-E power amplifiers (PA) with different output power are adopted in the design. In order to eliminate the phase mismatch of two paths, a continuously adjustable CMOS phase shifter with a predictable phase transfer function is added before each PA. Meanwhile, the drain modulation technique is presented to vary the voltage supply of the amplification unit. With the combination of drain modulation and parallel amplification, a wider range of output power is obtained than the previous one. The amplifiers work in 915MHz with the supply voltage of 1.8V and 2.5V. Simulation results show that the amplification unit could reach a maximum output power of 26dBm and maintain a power-added efficiency (PAE) higher than 40% over the 18dBm–26dBm output power range.

Integrated circuit (IC) design for a wireless BCI system is put forward in this paper. The system is composed of an electrode, a stimulator, antennas, and an integrated circuit including a preamplifier, an analog to digital converter (ADC), a current mode digital to analog converter (DAC), a transceiver and a micro control unit (MCU). The system is closed loop, which can detect and record electroencephalogram (EEG) signals, send the signals to computer wirelessly, and generate stimulating signals according to analysis results from the computer. A 16-bit ADC is designed and some non-idealities parameters (e.g. kT/C noise, 1/f Noise and so on) are given. Sub-threshold circuit technology is used to realize ultra low-power MCU. Both of the ADC and the MUC are verified by simulation results. Next work will include the design of the preamplifier, IDAC, and a single chip design integrating all the circuits.

By analyzing the features unfit for parallel computation and low power implementation, a VLSI architecture of JPEG-LS encoder for lossless image compression is proposed in this paper. It functionally consists of four parts: Mode decision module, clock controller, three linear parallel pipelines, and a two-tier data packer. Computations are organized in a fully pipelined style in these modules, so that real time data processing can be achieved. The clock management scheme with four interlaced clock domains and a dedicated clock controller is applied to ensure the bottleneck calculation, reduce the clock frequency on non-critical paths, and shut off the working clocks of idle modules, which reduces 15.7% of overall power consumption. The proposed JPEG-LS encoder with the features of low power and high processing speed, has been applied in a wireless endoscopy system.

Piezoelectric materials have been proposed as embedded power source, which are capable of converting mechanical energy into electrical energy. However, power generated from a piezoelectric material usually comes with poor characteristics such as high voltage, low current and high impedance. In order to drive the embedded sensor circuit, piezoelectric power needs to be characterized and regulated. In this paper, we present an analysis on the power generation characteristics of the stiff lead zirconate titanate (PZT) ceramics and its equivalent circuit. It is then verified by simulation and experimental results. Since a single PZT element may not meet the needs of real-world embedded applications, we present experiments and analysis using four identical PZTs. Finally, we outline an application where PZT elements are used for power generation in a Total Knee Replacement (TKR) implant.

A design of low power digital baseband for wireless endoscope capsule is presented. The key design issues involved in this IC are discussed, including implementation of communication protocol, real time image filter and real time JPEG-LS encoder. Power dissipation is lowered through the architectural exploration. The baseband has been implemented in 0.18 μm CMOS technology. Measurement results show that 50% power reduction is achieved when image compression is enabled @ 30 fps for VGA image at 1.2 V supply voltage compared with the situation when image compression is disabled, 11% power reduction is achieved compared with the previous research.

In this paper, a novel architecture of a fractional-Nphase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ΔΣ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) ΔΣ fractional-NPLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.

A 0.18mum CMOS 2.4GHz LNA (low noise amplifier) with digitally switchable capacitance has been designed to investigate its ability to compensate for performance variation across worst case process conditions. The effects of transistor model and passive component variation are first simulated to quantify the range of performance uncertainty. The use of various methods of switchable capacitance is then investigated at multiple LNA nodes to observe the effect on S11, S21, and NF. After calibration, the new design allows for 300MHz of frequency tuning and improvements in S11by 7.2dB, S21by 2.4dB, and NF by 0.6dB.

A capacitor switching technique for 1.5-bit/stage pipeline A/D converters is presented. This technique improves both integral nonlinearity (INL) and differential nonlinearity (DNL) performance due to capacitor mismatch. Monte Carlo simulation is carried out with all components' mismatches considered. The results show that the INL can be improved by 2.5 times and the DNL can be improved by 5 times. Comparing with the conventional capacitor mismatch calibration techniques, the proposed technique has the characteristics such as simple calibration circuits, undegraded conversion rate, and insensitive to the operation environment.

In this paper, a CMOS class-E power amplifier with power control is presented. Its output power could be varied over a broad range with high efficiency by utilizing the combination of the parallel amplification technique and the drain modulation technique. The drain modulation is implemented as a class-S modulator and the output powers of the parallel amplifiers are combined with quarter-wavelength transmission lines. The simulation results show that the power amplifier could achieves a maximum power-added efficiency (PAE) of 47.9% and maintain a PAE higher than 41% over the 140-700mW output power range.

This paper presents an incomplete settling design technique for switched-capacitor pipelined analog-to-digital converters (ADCs) to improve conversion rate. An improved multiplying digital-to-analog converter (MDAC) is introduced to eliminate the memory effect between adjacent samples in the conventional MDAC with insufficient settling time. The repeatable interstage gain error and nonlinearity due to incomplete settling are then corrected by a digital background calibration scheme. Behavioral simulations of two 13-bit incomplete settling ADCs, one with the improved MDACs and the other with the conventional MDACs, are performed in MATLAB to verify the proposed technique. The simulation results show that, the first ADC has an almost undegraded dynamic performance until the settling time decreases to 30% of the complete settling time, and at the point of 30% complete settling time, the improvement of SNDR and SFDR over the second one is 36.2dB and 52.4dBc, respectively.

This paper proposes a new low complexity near-lossless image compression method and its VLSI design for low power and high frame rate in the wireless endoscopy capsule system. Assuring outstanding compression performance and high image quality, the proposed method with the features of low complexity, low storage overhead and real time data processing, makes it ideal for hardware implementation. The VLSI architecture consists of two pipelined parts: The preprocessor and the JPEG-LS engine. A fully pipelined VLSI structure with a dedicated clock management scheme is proposed for the JPEG-LS engine, which ensures a low power application, and real time data processing as well. The hardware implementation has been verified on FPGA and implemented in 0.18μm CMOS technology.

A fully-differential 2-GHz phase-locked loop (PLL) was designed and fabricated in 0.18-μm CMOS process. The PLL rejects the common noise due to fully-differential VCO and differential charge pump. The VCO has a 16.15% tuning range (from 1.8998GHz to 2.2335GHz) due to a combination of analog and digital tuning technique (4-bit binary switch-capacitor array). With the pn-junction varactors, the phase noise of the VCO varies only about 2dB in the tuning range. The current consumption of the PLL is only about 6.1mA from a 1.8V power supply. It is comparable to the results reported in recent literatures. The phase noise of the PLL at 2.033GHz can achieve -117.17dBc/Hz at 1 MHz frequency offset from the carrier.

A full custom design of a three-stage amplifier is described in this paper. A feedback transconductance stage and a feedforward stage combined with two Miller compensation capacitors are used for frequency compensation. The circuit is designed in 0.18μm CMOS process with a 1.8V supply voltage. When driving a 150pF capacitive load, the amplifier achieves over l00dB de gain, 2.24MHz gain- bandwidth product (GBW), 62° phase margin (PM), 1.2V/μs slew rate (SR) and 61μW power dissipation. Compared to conventional multistage amplifiers, this work provides improvement in both GBW and SR, and also shows a significant improvement in MHz·pF/mW performance.

Cochlear implants have achieved great success in restoring hearing to profoundly deaf people. New generation implants pose more restrict requirements on processing precision and make traditional cochlear systems insufficient to deal with the large amount of data which should be transmitted via the wireless link. A new cochlear system with implant DSP is proposed to address the data rate problem. This system needs to transmit only voice-band signals with a data rate of 100 Kbps and the data rate bottleneck is removed for future development. By optimizing the speech processing algorithm and the inductive wireless link, the power consumption of this system increases less than 10% when compared with the traditional system.

A CMOS down-conversion micromixer for IEEE 802.11b WLAN transceivers is presented. The micromixer is a class-AB single-ended input double balanced mixer with on-chip bias loop. The operating principle of the CMOS micromixer is quantitively discussed and some design insights are given out. The mixer has been implemented in 0.18/spl mu/m CMOS process. The measured results show that the mixer achieves 1.5dB conversion gain, 12.2dB SSB NF, -1.5dBm input P1dB, 4dBm IIP3 with -16dB S11 (2.45GHz RF, 280MHz IF). The mixer draws 5.7mA current from a power supply of 1.8V.

This work presents the design and implementation of a 2.4GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25/spl mu/m CMOS process. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double balanced down-converter, band-pass filtered AGC loop and ASK detector) and a direct up-conversion transmitter analog front-end (20MHz IF PLL with well defined amplitude control circuit, ASK modulator, up-converter and output buffer) on a single chip together with an internal RF local oscillator and LO buffers. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. As a result, the IC operates from a power supply of 2.5 V, while only consuming 15mW in receiver (RX) mode and 14mW in transmitter (TX) mode.

This paper presents a curvature-compensated bandgap reference (BGR) circuit implemented in 0.35 /spl mu/m CMOS technology. The circuit delivers an output voltage of 1.09 V and achieves a temperature coefficient of 3.1 ppm//spl deg/C over [-20/spl deg/C, 100/spl deg/C] after trimming, a power supply rejection ratio of -80 dB at 1 KHz and an output noise level of 1.43 /spl mu/V/sqrt(Hz) at 1 KHz. The BGR circuit consumes a current of 37 /spl mu/A and the power supply ranges from 1.5 V to 3.3 V.

This paper proposes an open-source based 32-bit digital signal processor (DSP) suitable for embedded multimedia processing applications. The DSP is a MIPS-based scalar RISC with Harvard micro architecture, 5-stage integer pipeline and enhanced multimedia-processing capacity. It features a data path including non-aligned data access mechanism, two-dimensional DMA function and separated embedded instruction and data memories. This special architecture greatly promotes execution efficiency of boundary-crossed and block data access operations often found in multimedia processing. The processor achieves 80-MIPS performance with typical power dissipation of 88 mW. The prototype has been fabricated using UMC 0.18mum n-well 1P6M standard CMOS technology

In order to reduce the communication bandwidth and the transmitting power in the wireless endoscopy capsule, a high quality image compression algorithm has to be used. This paper proposes a new VLSI structure for the improved near-lossless color image compression algorithm to reduce the memory consumption 47% and save the power in the wireless endoscopy capsule. The improved compression algorithm can provide low average compression rate (2.12bits/pixel) with high image quality (larger than 53dB) for endoscopic images. The VLSI structure has been implemented in 0.18 /spl mu/m CMOS process.

A fifth-order elliptic low-pass Gm-C filter used in monolithic DAB receiver is presented, the filter integrates an on-chip frequency automatic tuning circuit based on PLL to control the cutoff frequency. The filter has been implemented in 0.25/spl mu/um CMOS process. The measurement results show that the frequency tuning error is within 1%, the dynamic range is 54dB, the stop-band rejection rate is greater than 40dB. The filter draws 13mA current from a 3.3V power supply.

This paper presents a fully integrated CMOS low-IF receiver working at L-band for DAB application. An image-rejection low noise amplifier (LNA) supplies over 30dB image rejection in the whole band. A calibration circuit improves matching of quadrature LO signals. Together with the quadrature weaver architecture, the receiver rejects the image signal more than 65dB. The receiver's noise figure is 4dB and OIP3 is 22dBm. The receiver is implemented in 0.25um CMOS process. The core die area is 9mm2.

This paper presents a new method for near-lossless image compression for digital colorful image sensors with Bayer color filter arrays (CFA). In this method, the captured CFA raw data is first smoothed by low-pass filters followed by down-sampling and then compressed directly before full color interpolation which introduces redundancy. Assuring high image quality, the method can provide higher compression ratio and lower complexity than conventional image compression methods and other existing similar methods. The composite peak signal to noise ratio (CPSNR) of the decompressed image is larger than 51 dB.

In order to decrease the communication bandwidth and save the transmitting power in the wireless endoscopy capsule, this paper presents a new near-lossless image compression algorithm suitable for hardware design based on the Bayer format image. This algorithm can provide low average compression rate (2.12 bits/pixel) with high image quality (larger than 53.11 dB) for endoscopic images. Especially, it has low complexity hardware overload and supports real-time compressing. In addition, the algorithm can provide lossless compression for the region of interest (ROI) and high quality compression for other regions. The ROI can be selected arbitrarily by varying ROI parameters.

Built on the biological neural network (BNN) theories, artificial neural network (ANN) has exhibited many significant advantages as of now. But yet, the high complexity of live beings' nervous system leads to quite limited knowledge on the working principles of learning, thinking and cognition at molecular level today, i.e. in a sense, the development of ANN has to be confined by the understanding of BNN. On the other hand, the huge memory space in an ANN chip for storing all connection weights is also a serious problem. In this paper, a novel mixed neural system interfacing biological neurons and semiconductor chip on a shared silicon wafer substrate for fast signal recognition is proposed, where three blocks are designed and interconnected. Recorded simulations with a 5 /spl times/ 5 microelectrode-array covered by a 100 /spl times/ 100 BNN show that combining the individual advantages of large-scale integrated circuits and BNN, this system has faster and more intelligent capabilities for fuzzy control, speech or pattern recognition as compared with common ways. At the same time, it can resolve the problems of huge memory space in ANN chips and the high complexity for algorithms, with an average 90.3% degree reduced efficiently between 5 trials.

By analysing the principle of multi-thresholded neurons (MTNs), a methodology is developed for designing multi-thresholded neuron circuits (MTNCs). First, two n-channel MOS transistors are employed to design the voltage-mode synapse circuit with high simplicity and linearity. Second, a BiCMOS technique based circuit named judgement-converting switch (JCS) is proposed. The JCS whose threshold is voltage-controlled current signal, provides an ability of converting the voltage signal to current signal. Based on this possibility, an approach is put forward to design multi-thresholded judgement function circuits (MTJFCs). Finally, single MTNC is designed for implementing XOR operation at switch level. Simulation results with PSPICE show that the designed circuits not only have the correct logic function but also small propagation delay.

Rate distortion optimization (RDO) plays an important role in a JPEG2000 encoder. An improved RDO algorithm is presented in this paper. The proposed algorithm is suitable for integrated circuit implementation and can reduce the computational cost. A hardware architecture which includes control unit, memory, divider, and data converter is also given to implement the algorithm. The circuit, based on the improved algorithm, has been integrated in a JPG2000 chip codec core.

This paper presents a new approach for near-lossless and lossless image compression in digital colorful image sensors with Bayer color filter arrays (CFAs). In this approach, the captured CFA raw data is firstly transformed from quincunx shape to rectangular shape and then smoothed by a low-pass filter. Lastly, the filtered data are compressed directly before full color than conventional interpolation-first image compression methods and other existing similar compression-first methods. Furthermore, through altering the quality control factor, the image quality, PSNR, can be changed from 44.15 dB to infinite with the compression ratio from averagely 3.3 bits/pixel to 6.9 bits/pixel.

A new adaptive step size adjustment least mean square (LMS) algorithm is presented. The proposed algorithm modifies the existing LMS using the estimated output error as an important component for the modification of the step size. Experiment results demonstrate that application of the new algorithm leads to a significant gain in SNR (signal-to-noise ratio), thus visibly reduces the output error and greatly improves the convergence speed in the context of adaptive active noise cancellation.

New methods for analog fault detection and for the selection of measurements for analog testing (wafer probe or final testing) are presented. Using Bayes' rule, the information contained in the measurement data and the information of the a priori probabilities of a circuit being fault free or faulty are converted into a posteriori probabilities and used for fault detection in analog integrated circuits, with a decision criterion that considers the statistical tolerances and mismatches of the circuit parameters. An adaptive formulation of the a priori probabilities is given that updates their values according to the results of the testing and fault detection. In addition, a systematic method is proposed for the optimal selection of the measurement components so as to minimize the probability of an erroneous test decision. Examples of DC wafer-probe testing as well as production testing using the power-supply current spectrum are given that demonstrate the effectiveness of the algorithms.

A novel method for the fault detection of analog circuits is proposed. Simple measurements are used to detect the possible faults in an analog circuit. Bayes decision rule is applied to combine the priori information and the information from testing. A sequential method to evaluate the value of the priori probability is given. Principle component analysis is applied for the calculation of the discrimination function in the case of the measurements being dependent. Examples are given to demonstrate the efficiency and the effectiveness of the algorithm.>