Goldstein filtering is a widely used phase filtering method for Interferometric Synthetic Aperture Radar (InSAR) processing for the purpose of noise reduction. While filtering methods can effectively reduce noise, we note that strong filters may produce artifact features shown as cross-like patterns in interferograms. In this paper, the adjustable parameters of Goldstein filtering in the Sentinel Application Platform (SNAP) software are explored, and InSAR-derived DEMs were generated to investigate how each parameter influences interferograms and whether the cross-like patterns are adverse features for InSAR processing. The results showed that adaptive filter exponent and FFT size are the most influential parameters that significantly affect the strength of Goldstein filters. Furthermore, our findings imply that the presence of cross-like patterns has a negative impact on InSAR processing. As the default values for Goldstein filtering in the SNAP software are excessively high and frequently exhibits cross-like patterns, we suggest users to modify the adaptive filter exponent to a value of 0.5-0.6.

The printed circuit board (PCB) routing problem has been studied extensively in recent years. Due to continually growing net/pin counts, extremely high pin density, and unique physical constraints, the manual routing of PCBs has become a time-consuming task to reach design closure. Previous works break down the problem into escape routing and area routing and focus on these problems separately. However, there is always a gap between these two problems requiring a massive amount of human efforts to fine-tune the algorithms back and forth. Besides, previous works of area routing mainly focus on routing between escaping routed ball-grid-array (BGA) packages. Nevertheless, in practice, many components are not in the form of BGA packages, such as passive devices, decoupling capacitors, and through-hole pin arrays. To mitigate the deficiencies of previous works, we propose a full-board routing algorithm that can handle multiple real-world complicated constraints to facilitate the printed circuit board routing and produce high-quality manufacturable layouts. Experimental results show that our algorithm is effective and efficient. Specifically, for all given test cases, our router can achieve 100% routability without any design rule violation while the other two state-of-the-art routers fail to complete the routing for some test cases and incur design rule violations.

Mixed-cell-height circuits have prevailed in advanced technology to address various design requirements. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: 1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads and 2) mixed-height-cell perturbation could cause severe inter-row MIA violations. This article addresses the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intrarow violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Experimental results show that our algorithm can efficiently solve all MIA violations without any extra area overhead.

Data augmentation plays a crucial role in training a CNN-based detector. Most previous approaches were based on using a combination of general image-processing operations and could only produce limited plausible image variations. Recently, GAN (Generative Adversarial Network) based methods have shown compelling visual results. However, they are prone to fail at preserving image-objects and maintaining translation consistency when faced with large and complex domain shifts, such as day-to-night. In this paper, we propose AugGAN, a GAN-based data augmenter which could transform on-road driving images to a desired domain while image-objects would be well-preserved. The contribution of this work is three-fold: (1) we design a structure-aware unpaired image-to-image translation network which learns the latent data transformation across different domains while artifacts in the transformed images are greatly reduced; (2) we quantitatively prove that the domain adaptation capability of a vehicle detector is not limited by its training data; (3) our object-preserving network provides significant performance gain in the difficult day-to-night case in terms of vehicle detection. AugGAN could generate more visually plausible images compared to competing methods on different on-road image translation tasks across domains. In addition, we quantitatively evaluate different methods by training Faster R-CNN and YOLO with datasets generated from the transformed results and demonstrate significant improvement on the object detection accuracies by using the proposed AugGAN model.

Unpaired image-to-image translation is proven quite effective in boosting a CNN-based object detector for a different domain by means of data augmentation that can well preserve the image-objects in the translated images. Recently, multimodal GAN (Generative Adversarial Network) models have been proposed and were expected to further boost the detector accuracy by generating a diverse collection of images in the target domain, given only a single/labelled image in the source domain. However, images generated by multimodal GANs would achieve even worse detection accuracy than the ones by a unimodal GAN with better object preservation. In this work, we introduce cycle-structure consistency for generating diverse and structure-preserved translated images across complex domains, such as between day and night, for object detector training. Qualitative results show that our model, Multimodal AugGAN, can generate diverse and realistic images for the target domain. For quantitative comparisons, we evaluate other competing methods and ours by using the generated images to train YOLO, Faster R-CNN and FCN models and prove that our model achieves significant improvement and outperforms other methods on the detection accuracies and the FCN scores. Also, we demonstrate that our model could provide more diverse object appearances in the target domain through comparison on the perceptual distance metric.

For circuit designs in advanced technologies, standard-cell libraries consist of cells with different heights; for example, the number of fins determines the height of cells in the FinFET technology. Cells of larger heights give higher drive strengths, but consume larger areas and power. Such mixed cell heights incur new, complicated challenges for layout designs, due mainly to the heterogeneity in cell dimensions and thus their larger solution spaces. There is not much published work on layout designs with mixed-height standard cells. This paper addresses the legalization problem of mixed-height standard cells, which intends to place cells without any overlap and with minimized displacement. We first study the properties of Abacus, generally considered the best legalization method for traditional single-row-height standard cells but criticized not suitable for handling the new challenge, analyze the capability and insufficiencies of Abacus for tackling the new problem, and remedy Abacuss insufficiencies and extend its advantages to develop an effective and efficient algorithm for the addressed problem. For example, dead spaces become a critical issue in mixed-cell-height legalization, which cannot be handled well with an Abacus variant alone. We thus derive a dead-space-aware objective function and an optimization scheme to handle this issue. Experimental results show that our algorithm can achieve the best wirelength among all published methods in reasonable running time, e.g., about 50% smaller wirelength increase than a state-of-the-art work.

Mixed-cell-height circuits have prevailed in advanced technology to address various design needs. Along with device scaling, complex minimum-implant-area (MIA) constraints arise as an emerging challenge in modern circuit designs, adding to the difficulties in mixed-cell-height placement. Existing MIA-aware detailed placement with single-row-height standard cells is insufficient for mixed-cell-height designs: (1) filler insertion, typically used to resolve MIA violations, might incur unaffordable area and wirelength overheads, and (2) mixed-height cell perturbation could cause severe inter-row MIA violations. This paper presents the first work to address the mixed-cell-height detailed placement problem considering both intra- and inter-row MIA constraints. We first fix intra-row violations by clustering violating mixed-height cells of the same threshold voltage, and then perturb each cluster to obtain a desired cell permutation by applying an efficient, optimal dynamic-programming-based algorithm for a special case and Algorithm DLX for general ones, where a provably constant performance ratio for a mixed-cell-height reshaping problem can be achieved. With a network-flow-based formulation, remaining violating cells are placed in appropriate filler-insertion positions to fix cell violations and minimize area. After performing mixed-cell-height detailed placement, we finally fix inter-row violations by shifting violating cells in minimum displacement. Compared with a filler insertion method and a greedy clustering approach, experimental results show that our proposed algorithm can resolve all MIA violations with smallest HPWL and area overheads in reasonable running time.