The shrinking of technology nodes has led to high density memories containing large amounts of transistors which are prone to defects and reliability issues. Their test is generally based on the use of well-known March algorithms targeting Functional Fault Models (FFMs). This paper presents a novel approach for memory testing which relies on Cell-Aware (CA) methodology to further improve the yield of System on Chips (SoCs). Consequently, using CA methodology converts memory testing from functional to structural testing. In this work, the preliminary flow of the CA-based memory testing methodology is presented. The generation of the CA model for the SRAM bit cell has been demonstrated as a case study. The generated CA model and the structural representation of the memory are used by the ATPG to test the bit cell in the presence of short and open defects. The generated test patterns are able to detect both static and dynamic faults in the bit cell with a test coverage of 100%.

As the semiconductor industry continues to shrink the transistor feature size, new fault models need to be invented and deployed to ensure manufacturing test and diagnostic of the highest quality. The Cell-Aware (CA) test and diagnosis methodology targets the detection of defects inside standard (std) cells, at the transistor level. While becoming an industry standard, the CA methodology, has a large and costly deployment overhead, involving numerous analog simulations. In [1], we presented an innovative flow using Machine-Learning (ML) to reduce the CA test method runtime and ease its adoption for industrial usage. Experiments using different technology nodes demonstrated an over 99% runtime reduction for 80% of combinational cells. In this paper, new elements are presented to more widely take advantage of the ML flow for CA characterization. This includes a new decision algorithm, leveraging ML techniques to decide whether the CA characterization of a new std cell should be ML-based or simulation-based, thus allowing to decrease the CA characterization runtime while maintaining high quality CA models for all cells. Experimental results demonstrate the high performance of the new decision algorithm. The fault coverage on real cell-internal defects of ATPG patterns using ML predicted CA data proves that our predicted CA data can accurately replace those obtained by running extensive analog simulations, thus proving the effectiveness and pertinence of the proposed methodology.

Cell-aware model generation refers to the process of characterizing cell-internal defects, a key step to ensure high test and diagnosis quality. The main limitation of this process is the generation effort, which is costly in terms of run time, SPICE simulator license usage and flow complexity. in this work, a methodology that does not use any electrical defect simulation is developed to predict the response of a cell-internal defect once it is injected in a standard cell. More widely, the aim is to use existing cell-aware models from various standard cell libraries and technologies to predict cell-aware models for new standard cells independently of the technology. A Random Forest classification algorithm is used for prediction. Experiments on several cell libraries using different technologies demonstrate the accuracy and performance of the method. The paper concludes by the presentation of a new hybrid CA model generation flow.

In this paper, we propose a new framework for cell-aware defect diagnosis of customer returns based on supervised learning. The proposed method comprehensively deals with static and dynamic defects that may occur in real circuits. A Naive Bayes classifier is used to precisely identify defect candidates. Results obtained on benchmark circuits, and comparison with a commercial cell-aware diagnosis tool, demonstrate the efficiency of the proposed approach in terms of accuracy and resolution.

Diagnosis is crucial in order to establish the root cause of observed failures in Systems-on-Chip (SoC). In this paper, we present a new framework based on supervised learning for cell-aware defect diagnosis of customer returns. By using a Naive Bayes classifier to accurately identify defect candidates, the proposed flow indistinctly deals with static and dynamic defects that may occur in actual circuits. Results achieved on benchmark circuits, as well as comparison with a commercial cell-aware diagnosis tool, show the effectiveness of the proposed framework in terms of accuracy and resolution. Moreover, the proposed flow has been experimented and validated on industrial circuits (two test chips and one customer return from STMicroelectronics), thus corroborating the results achieved on benchmark circuits.

In critical (e.g. automotive) applications, Systems-on-Chip (SoC) failures that occurred during mission mode (in the field) are the most critical since they may lead to catastrophic effects. In this context, diagnosis is crucial in order to establish the root cause of observed failures with the best accuracy. With the advent of very deep submicron technologies (i.e. 7 nm), achieving such level of accuracy will become more and more difficult with today's intra-cell diagnosis tools based on effect-cause or cause-effect paradigms. This will compromise the success of subsequent Physical Failure Analysis (PFA) done on defective SoCs. Machine Learning (ML) is now used in numerous classification problems where the knowledge on some data can be used to classify a new instance of such data. In particular, several ML-based solutions exist to address volume diagnosis for yield improvement. These learning-guided diagnosis approaches start from an existing set of defect candidates and try to minimize this set (eliminate bad candidates) owing to the use of ML tools and numerous data collected during production test (e.g. thousands of failed chips with candidates correctly labeled). Although efficient in volume diagnosis, these approaches cannot be used to identify the root cause of failures in customer returns, since only one failed chip is investigated in this case, with no information about the defective behavior of some other similar chips used in the same conditions (environment, workload, etc.). In this paper, we propose a new learning-guided approach for diagnosis of mission mode failures in customer returns. The proposed approach directly produces a minimum set of good candidates derived from the application of the learning-guided intra-cell diagnosis flow. Results obtained on a set of benchmark circuits, and comparison with a commercial intra-cell diagnosis tool, show the feasibility, effectiveness and accuracy of the proposed approach.

Improving diagnosis resolution becomes very important in nanometer technology. Nowadays, defects are affecting gate and transistor level. In this paper, we present a new method to volume diagnosis intra-gate defects affecting standard cell Integrated Circuits (ICs). Our method can identify the cause of failure of different intra-gate defects such as bridge, open and resistive-open defects. Our method gives accurate results since it is based on the use of physical information extracted from library cells layout. Our method can also locate intra-gate defects in presence of multiple faults. Experimental results show the efficiency of our approach to isolate injected defects on industrial designs.