A large number of algorithms for multidimensional signals processing and scientific computation come in the form of iterative stencil loops (ISLs), whose data dependencies span across multiple iterations. Because of their complex inner structure, automatic hardware acceleration of such algorithms is traditionally considered as a difficult task. In this paper, we introduce an automatic design flow that identifies, in a wide family of bidimensional data processing algorithms, subportions that exhibit a kind of parallelism close to that of ISLs; these are mapped onto a space of highly optimized ad-hoc architectures, which is efficiently explored to identify the best implementations with respect to both area and throughput. Experimental results show that the proposed methodology generates circuits whose performance is comparable to that of manually optimized solutions, and orders of magnitude higher than those generated by commercial high-level synthesis tools.

The performance and the efficiency of recent computing platforms have been deeply influenced by the widespread adoption of hardware accelerators, such as graphics processing units (GPUs) or field-programmable gate arrays (FPGAs), which are often employed to support the tasks of general-purpose processors (GPPs). One of the main advantages of these accelerators over their sequential counterparts (GPPs) is their ability to perform massive parallel computation. However, to exploit this competitive edge, it is necessary to extract the parallelism from the target algorithm to be executed, which generally is a very challenging task. This concept is demonstrated, for instance, by the poor performance achieved on relevant multimedia algorithms, such as Chambolle, which is a well-known algorithm employed for the optical flow estimation. The implementations of this algorithm that can be found in the state of the art are generally based on GPUs but barely improve the performance that can be obtained with a powerful GPP. In this article, we propose a novel approach to extract the parallelism from computation-intensive multimedia algorithms, which includes an analysis of their dependency schema and an assessment of their data reuse. We then perform a thorough analysis of the Chambolle algorithm, providing a formal proof of its inner data dependencies and locality properties. Then, we exploit the considerations drawn from this analysis by proposing an architectural template that takes advantage of the fine-grained parallelism of FPGA devices. Moreover, since the proposed template can be instantiated with different parameters, we also propose a design metric, the expansion rate, to help the designer in the estimation of the efficiency and performance of the different instances, making it possible to select the right one before the implementation phase. We finally show, by means of experimental results, how the proposed analysis and parallelization approach leads to the design of efficient and high-performance FPGA-based implementations that are orders of magnitude faster than the state-of-the-art ones.

FPGA systems are moving towards a system-on-chip model, both at the architectural level and in the development tools. Developers are able to design and implement IP using a mixture of HLS, RTL, and software, then integrate them with third-party IP cores and hardened CPUs using one or more shared memory buses. This allows functionality to be easily connected together at the bus level, but accessing IP core functionality requires designers to support each component's protocol and co-ordinate hardware from a CPU. This paper presents a protocol called PushPush, which allows HLS, RTL, and software components to expose functionality as strongly typed functions, and allows any component to access functions exposed by any other component in the system. The protocol is designed for maximum efficiency in memory buses such as AXI and Avalon, reducing each function call to two burst writes delivering both data and control, minimising bus traffic and eliminating the need for global polling or interrupt delivery. We demonstrate this approach in a Zynq environment, using components written in C++ (ARM/Linux), C (Microblaze), Vivado HLS (Logic), and Verity (Logic). We show that any component can call functions exposed by any other component, without knowing where or how that function is located. Performance is at least 1 million function calls/sec between any pair of components, and rises to 4 million function calls/sec between pairs of Vivado HLS components.

Latest embedded bio-signal analysis applications, targeting low-power Wireless Body Sensor Nodes (WBSNs), present conflicting requirements. On one hand, bio-signal analysis applications are continuously increasing their demand for high computing capabilities. On the other hand, long-term signal processing in WBSNs must be provided within their highly constrained energy budget. In this context, parallel processing effectively increases the power efficiency of WBSNs, but only if the execution can be properly synchronized among computing elements. To address this challenge, in this work we propose a hardware/software approach to synchronize the execution of bio-signal processing applications in multi-core WBSNs. This new approach requires little hardware resources and very few adaptations in the source code. Moreover, it provides the necessary flexibility to execute applications with an arbitrarily large degree of complexity and parallelism, enabling considerable reductions in power consumption for all multi-core WBSN execution conditions. Experimental results show that a multi-core WBSN architecture using the illustrated approach can obtain energy savings of up to 40%, with respect to an equivalent single-core architecture, when performing advanced bio-signal analysis.

Activity recognition has been a research field of high interest over the last years, and it finds application in the medical domain, as well as personal healthcare monitoring during daily home- and sports-activities. With the aim of producing minimum discomfort while performing supervision of subjects, miniaturized networks of low-power wireless nodes are typically deployed on the body to gather and transmit physiological data, thus forming a Wireless Body Sensor Network (WBSN). In this work, we propose a WBSN for online activity monitoring, which combines the sensing capabilities of wearable nodes and the high computational resources of modern smart phones. The proposed solution provides different tradeoffs between classification accuracy and energy consumption, thanks to different workloads assigned to the nodes and to the mobile phone in different network configurations. In particular, our WBSN is able to achieve very high activity recognition accuracies (up to 97.2%) on multiple subjects, while significantly reducing the sampling frequency and the volume of transmitted data with respect to other state-of-the-art solutions.

Reconfigurable platforms are a promising technology that offers an interesting trade-off between flexibility and performance, which many recent embedded system applications demand, especially in fields such as multimedia processing. These applications typically involve multiple ad-hoc tasks for hardware acceleration, which are usually represented using formalisms such as Data Flow Diagrams (DFDs), Data Flow Graphs (DFGs), Control and Data Flow Graphs (CDFGs) or Petri Nets. However, none of these models is able to capture at the same time the pipeline behavior between tasks (that therefore can coexist in order to minimize the application execution time), their communication patterns, and their data dependencies. This article proves that the knowledge of all this information can be effectively exploited to reduce the resource requirements and the timing performance of modern reconfigurable systems, where a set of hardware accelerators is used to support the computation. For this purpose, this article proposes a novel task representation model, named Temporal Constrained Data Flow Diagram (TCDFD), which includes all this information. This article also presents a mapping-scheduling algorithm that is able to take advantage of the new TCDFD model. It aims at minimizing the dynamic reconfiguration overhead while meeting the communication requirements among the tasks. Experimental results show that the presented approach achieves up to 75% of resources saving and up to 89% of reconfiguration overhead reduction with respect to other state-of-the-art techniques for reconfigurable platforms.

The automatic generation of hardware implementations for a given algorithm is generally a difficult task, especially when data dependencies span across multiple iterations such as in iterative stencil loops (ISLs). In this paper, we introduce an automatic design flow to extract parallelism from an ISL algorithm and perform a design space exploration to identify its best FPGA hardware implementation, in terms of both area and throughput. Experimental results show that the proposed methodology generates hardware designs whose performance is comparable to the one of manually-optimized solutions, and orders of magnitude higher than the implementations generated by commercial high-level synthesis tools.

Wireless Sensor Networks (WSNs) are particular networks characterized by limited energy and computational resources and, if their transmission range is limited to a person's area, they are known as Body Area Networks (BANs). When two or more BANs are co-located and operate on the same channel, active periods can overlap and transmissions can conflict. This phenomenon, that drastically reduces performances and reliability of BANs, is known as BAN-BAN interference. In order to solve this issue, it is possible to employ techniques such as channel switching. However, channel switching is not suitable if the amount of channels is lower than the amount co-located BANs and, considering that interferences of Zigbee/802.15.4 networks with other technologies like 802.11 or Bluetooth reduce the amount of channels available for communication, an alternative approach is required. This paper introduces a BAN-BAN Interference Reduction System (B2IRS) which reschedules beacon packets in order to avoid active period overlap, reducing the interferences between distinct BANs. This approach is complementary to channel switching since it works with single-channel interferences, that arise when no free channels are available anymore. Experimental results, conducted comparing our methodology with the original IEEE 802.15.4, show that B2IRS is able to effectively reduce BAN-BAN interference, making it possible to almost maintain the same performance and energy consumption of an ideal situation (without interferences).

Wireless sensor networks (WNSs) are gradually evolving from a promising technology to a well-established reality in a large set of different domains. In order to fulfill the requirements of the specific scenario, a WSN must provide the right tradeoff between performance and lifetime, which is heavily determined by the network design. However, although the complexity of WSNs is increasing, the design space exploration is often carried out manually without the support of a general analytical methodology. In this paper, we advocate a model-based approach as an efficient and scalable way to explore the energy-performance tradeoffs during the design. In particular, we show that it is possible to define system-level models to describe wide classes of WSNs, providing a quick and accurate network evaluation. As a proof of concept, we propose a general model that describes the main characteristics of a class of WSNs for human health monitoring, and we apply it to a real case study. The results show that the energy-performance estimation error of the model never exceeds 1.74% compared to real data, while the evaluation time is reduced by up to 6 orders of magnitude with respect to an accurate network simulation.

This paper introduces Tacit Consent (TaCo), a technique that exploits spatial correlation in Wireless Sensor Networks in order to reduce energy consumption while maintaining a very high accuracy on the measured data. In fact, nodes densely deployed in a field of interest are proved to sense highly correlated data, thus this intrinsic redundancy can be exploited to predict the neighbors' measurements by defining custom estimation functions, which aim at replicating the relationship between the data sensed by two nodes. To exploit spatial correlation, TaCo splits the nodes into two groups: representative and member nodes. Representative nodes directly transmit their measurements, while member nodes use overhearing to understand whether additional information is required. If the estimation function correctly predicts the measurements of the member nodes, they tacitly consent the estimation without performing any transmission. Differently from the other state-of-the-art approaches, such as the YEAST algorithm, TaCo can be used on top of existing routing and clustering protocols. Experimental results prove that TaCo is able to drastically reduce the energy consumption of the network when a high precision of the measured data is required.

The determination of the optical flow is a central problem in image processing, as it allows to describe how an image changes over time by means of a numerical vector field. The estimation of the optical flow is however a very complex problem, which has been faced using many different mathematical approaches. A large body of work has been recently published about variational methods, following the technique for total variation minimization proposed by Chambolle. Still, their hardware implementations do not offer good performance in terms of frames that can be processed per time unit, mainly because of the complex dependency scheme among the data. In this work, we propose a highly parallel and accelerated FPGA implementation of the Chambolle algorithm, which splits the original image into a set of overlapping sub-frames and efficiently exploits the reuse of intermediate results. We validate our hardware on large frames (up to 1024 × 768), and the proposed approach significantly improves state-of-the-art implementations, reaching up to 76× speedups, which enables real-time frame rates even at high resolutions.

Reconfigurable computing is a promising technology that offers an interesting trade-off between flexibility and performance, which many recent multi-core embedded system applications demand. In order to achieve these objectives, it is necessary to optimize the deployment of the hardware cores on the FPGA platform, trying to reduce the reconfiguration overhead while meeting the desired performance. In this paper, we propose a hybrid mapping and scheduling technique for multi-core applications on reconfigurable devices, which exploits the information about the relationships among the application cores to minimize the overhead due to reconfiguration.

Nowadays, multi-core systems-on-chip (SoCs) are typically required to execute multiple complex applications, which demand a large set of heterogeneous hardware cores with different sizes. In this context, the popularity of dynamically reconfigurable platforms is growing, as they increase the ability of the initial design to adapt to future modifications. This paper presents a design flow to efficiently map multiple multi-core applications on a dynamically reconfigurable SoC. The proposed methodology is tailored for a reconfigurable hardware architecture based on a flexible communication infrastructure, and exploits applications similarities to obtain an effective mapping. We also introduce a run-time mapper that is able to introduce new applications that were not known at design-time, preserving the mapping of the original system. We apply our design flow to a real-world multimedia case study and to a set of synthetic benchmarks, showing that it is actually able to extract similarities among the applications, as it achieves an average improvement of 29% in terms of reconfiguration latency with respect to a communication-oriented approach, while preserving the same communication performance.

The role of Field-Programmable Gate Arrays (FPGAs) in System-on-Chip (SoC) design considerably increased in the last few years. Their established importance is due to the large amount of hardware resources they offer, as well as to their increasing performance, and furthermore to the support for reconfigurability. Even though FPGAs seem to have reached their maturity, there is still a lack of Computer-Aided Design (CAD) tools able to deal with dynamic reconfiguration. Existing algorithms aim at optimizing the performance of a set of applications, basing the computation on classic metrics (such as communication overhead), while reconfiguration-related issues are not taken into consideration. This work proposes a design methodology to map several applications on the FPGA area at run-time. Starting from a basic solution found at design-time for the initial set of applications, the proposed algorithm makes it possible to map a new application (not known at design-time), both minimizing the number of synthesis processes and optimizing the on-chip performance of the new application. Experimental results show that the proposed approach is able to achieve up to a 18% reduction in the number of reconfigurations with respect to an off-line static-mapping approach, while generally preserving the performance of the executed applications on the FPGA.

The increasing amount of programmable logic provided by modern FPGAs makes it possible to execute multiple hardware applications on the same device. This approach is reinforced by dynamic reconfiguration, which allows a single part of the device to be configured with a single hardware module. The proposed solution is a Linux-based operating system to manage on-demand module configuration on an FPGA while providing a set of high-level abstractions to user applications. The proposed approach has been validated in a cryptographic context using the DES and the AES algorithms.