Demo Data from EDBT 2026 / reviewers in the wild / expert
Kelin J. Kuhn
dblp:66/7450
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 2009
—ORCID · unresolved
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Integrated circuit design · 100% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design › technology scaling
CMOS scaling |
0.1 | 1 | 2009 | CMOS scaling beyond 32nm: challenges and opportunities · DAC 2009 |
Integrated circuit design › semiconductor device fabrication
CMOS technology |
0.1 | 1 | 2009 | CMOS scaling beyond 32nm: challenges and opportunities · DAC 2009 |
Integrated circuit design › semiconductor devices
multi-gate devices |
0.1 | 1 | 2009 | CMOS scaling beyond 32nm: challenges and opportunities · DAC 2009 |
Integrated circuit design › semiconductor devices › semiconductor device design
transistor design |
0.1 | 1 | 2009 | CMOS scaling beyond 32nm: challenges and opportunities · DAC 2009 |
Integrated circuit design
low-power circuit design |
0.0 | 1 | 2009 | CMOS scaling beyond 32nm: challenges and opportunities · DAC 2009 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | CMOS scaling beyond 32nm: challenges and opportunitiesabstractThis paper explores the challenges and opportunities facing CMOS process generations past the 32nm technology node. Planar and multiple-gate devices are compared and contrasted. Resistance and capacitance challenges are reviewed in relation to past history and on-going research. Key enhancers such as high-k metal-gate (HiK-MG), substrate and channel orientation, and NMOS and PMOS strain, are discussed in relation to the challenges of the coming transistor generations. Kelin J. Kuhn |
DAC | 1 |