There has been significant interest in hardware-assisted deterministic Record and Replay (RnR) systems for multithreaded programs on multiprocessors. However, no proposal has implemented this technique in a hardware prototype with full operating system support. Such an implementation is needed to assess RnR practicality.

In this paper we present a scalable wormhole switch architecture with a credit based guaranteed service implementation. By means of credits for a service guarantee the architecture is also able to deal with mesochronous GALS systems. We extended a regular wormhole switch architecture with a control unit for service configuration during run-time and modified the arbitration policy. These changes result in a marginal area overhead per switch of approximately 4\%. Thus our new architecture provides a simple solution to implement service guarantees without limitation to a fully synchronous system. We synthesized our design with a 65nm technology and achieved a clock frequency of 1GHz. Due to the high clock frequency we are able to get a channel throughput of more than 4GB/sec whereas the total design complexity is 30k gate equivalents.