We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Write-ability is further enhanced by an Adaptive Data-Aware Write-Assist (ADAWA) scheme. The 1.0Mb test chip operates from 1.5V to 0.7V, with operating frequency of [email protected] and 25°C. The measured power consumption is 23.21mW (Active)/2.42mW (Leakage) at 1.2V, TT, 25°C; and 6.01mW (Active)/0.35mW (Leakage) at 0.7V, TT, 25°C.

This paper presents a march-like testTAC-Pto cover comparison faults of ternary content addressable memories (TCAMs) with asymmetric cells. The TAC-Ponly requires 4NWrite operations and (3N+2B) Compare operations for anN×B-bit TCAM with Hit and priority address encoder outputs. We show that the test also can cover search time failures induced by process variation in the comparison circuit of a TCAM. Furthermore, a test TMFfor match failures induced by the process variation in the comparison circuit of a TCAM is also presented.

Ternary content addressable memory (TCAM) is a key component in various applications for its fast lookup operation. Symmetric and asymmetric TCAM cells are two widely used cells for implementing a TCAM array. This paper presents several comparison fault models of TCAMs with asymmetric cells based on electrical defects. Some new comparison faults which do not exist in a TCAM with symmetric cells are found. A march-like test algorithm is also proposed to cover the defined comparison faults. The test algorithm consists of 8N Write operations and (3N + 2B) Compare operations for an N×B-bit TCAM with Hit output only.