With the increasing demand for Artificial Intelligence (AI) applications in Internet of Things (IoT) edge devices, accelerating Deep Neural Network (DNN) inference has become a critical challenge, especially for structured sparse models deployed in resource-constrained environments. Most prior accelerators only target weight sparsity while overlooking activation sparsity, and rarely support multiple N:M sparsity levels. This paper introduces Sparse Tensor Product Element (STPE), a novel Processing Element (PE) tailored for fine-grained N:M structured sparse matrix multiplication to improve multiplier utilization. STPE leverages a shared-register and dynamic multiplier allocation strategy to improve Multiply-Accumulate (MAC) unit utilization under sparsity constraints typical in IoT deployment scenarios. The proposed STPE array architecture integrates STPEs with an Indexing Module (IM), which dynamically schedules input activations and ensures computation validity within the constraints of hardware MAC limits. We applied N:M structured pruning to AlexNet, ResNet50, and VGG16. Under TSMC 40nm technology, the proposed architecture demonstrated up to 5.3× speedup, 5× area efficiency, and 3.5× energy efficiency compared to conventional systolic arrays, making it well-suited for deployment in IoT devices and edge computing scenarios.

Audio super-resolution (ASR) restores missing high-frequency content from low-bandwidth speech, which frequently arises in IoT acoustic sensing and edge voice interfaces due to power, bandwidth, and latency constraints. Recent Mamba-based models improve long-range modeling efficiency but are often adapted from vision templates and are not optimized for ASR deployment. We propose UPVM-ASR, an ultralight dual-stream U-Net built on VMamba visual state-space (VSS) blocks to reconstruct magnitude and phase spectrograms in parallel. A channel-parallel, weight-shared selective-scan design (PVSS) reduces parameter redundancy while retaining global-local spectro-temporal modeling with linear complexity. UPVM-ASR is highly compact, achieving 0.41M parameters and 1.00 GFLOP, and remains competitive across 16 kHz and 48 kHz targets on the VCTK dataset. UPVM-ASR attains the lowest log-spectral distance (LSD) in the most challenging settings (from 2 kHz to 16 kHz and from 8 kHz to 48 kHz) while maintaining strong ViSQOL and STOI scores. These results indicate that optimized lightweight state-space U-Nets can deliver high-fidelity ASR under tight compute and communication budgets. Furthermore, to assess deployment and robustness, we additionally provide a deployment-oriented pure C implementation and benchmark runtime on embedded platforms, as well as report results under noisy/out-of-domain conditions on VCTK-DEMAND and NISQA datasets.

Deep learning has been the state-of-the-art for transforming an image into its energy-aware version to lower the display power consumption of organic light-emitting diode (OLED). Most of the existing works achieve high-quality metrics resorting to high computation cost. Moreover, under an intense power-saving rate, the quality degradation of the power-aware image becomes more severe. In this work, we propose a novel training strategy for a deep neural network that explicitly address the degradation that occurs in power-aware image in which the intensity distribution is shrunk and shifted to a lower intensity. Our training strategy, referred to as power-preserving degradation (PPD), deliberately obstructs the distribution of the intensity and the details of an input image in the training phase. Hence, the network learns to optimize the utilization of dynamic range and quality metrics. In addition, the power-preserving term mitigates the power error due to the change in the distribution. We pair our training strategy with a simple and lightweight network that processes the input in two stages. The input is decomposed into a feature set, and a power-attention mechanism is applied to reduce intensity with on-demand power. We experiment with high power-saving rates of 40%, 50%, 60%, and 70% on three image datasets. As a result, our proposed strategy predominantly obtains the highest scores metrics. For instance, under 70% power-saving, it achieves a $$\sim$$ 0.85 structural similarity score.

Accurate segmentation of medical images, particularly for anatomical structures with irregular shapes and low contrast such as the esophagus, remains a significant challenge. To address this issue, we propose MEM-UNet, a robust 3D Mamba-based UNet framework enhanced by mathematical morphology. Our approach adapts the State Space Model (SSM) in Mamba to support three-dimensional CT volumes, establishing an effective 3D perception backbone for the UNet architecture. In addition, we incorporate Morphology-Aware Spatial-Channel Attention (MASCA) blocks into the skip connections, where Morphology-Enhanced Spatial Convolution (MESC) augments spatial representations while Squeeze-and-Excitation (SE) highlights channel-wise features. This integration effectively leverages the shape-awareness provided by morphological operations, thus improving boundary precision. To further refine segmentation, we introduce a Morphology-Enhanced Decision (MED) layer that sharpens contour boundaries and performs voxel-level classification with high precision. Extensive experiments on SegTHOR and BTCV datasets demonstrate that MEM-UNet surpasses state-of-the-art models, achieving Dice Similarity Coefficient (DSC) scores of 87.42% and 74.86% for multi-organ segmentation, and 78.94% and 67.70% for esophagus segmentation, respectively. Ablation studies confirm the effectiveness of the proposed components and highlight the benefits of integrating mathematical morphology into our pipeline.

People with hearing impairments use visual cues through lipreading to get a better understanding of their communication. While many studies focus on lipreading research for English and Mandarin, there are still limited studies that address lipreading research for low-resource languages. Therefore, we establish a novel framework based on deep learning to solve the problem, which consists of several key components. First, it includes an optimized preprocessing stage and additional data augmentation for the lipreading task. Second, it incorporates a Spatial-Temporal Feature Extractor (STFE) to extract better lip movement features. Our STFE uses a channel and spatial attention module incorporated with ResNet-18 as an attention-enhanced ResNet and a combination of BiGRU with a multi-stage residual transformer encoder. Lastly, the model integrates a word classification module to make the final prediction. Moreover, we train the model using the quantity-ratio curriculum learning strategy by starting with easier categories and incrementally increasing difficulty. It maintains constant exposure to easier samples while gradually introducing more difficult ones until reaching the final stage with a defined quantity. In addition, we also present an expanded lipreading dataset for the Indonesian language (ID-LR), which is one of the low-resource languages. ID-LR contains more than 105,000 videos with 230-word classes spoken by diverse persons in natural conditions. With this configuration and learning strategy, our approach reaches remarkable performance in terms of accuracy and becomes state-of-the-art in multiple low-resource languages of lipreading datasets (Turkish, Romanian, German, and Indonesian) based on our presented benchmarks.

Recently, deep learning has been widely employed across various domains. The Convolution Neural Network (CNN), a popular deep learning algorithm, has been successfully utilized in object recognition tasks, such as face recognition, vehicle recognition, and license plate recognition. However, conventional methods for object recognition may not be appropriate for low-light image recognition due to information loss in the dark regions and unexpected noise that can impair object quality. Therefore, the development of specialized techniques for low-light image enhancement has become a major research focus for object detection. This paper proposed a gradient-based saliency map detection method with an improved ResNet architecture that outperforms previous works in detecting multiple or large objects. Additionally, the proposed method enhances images with the object as the center and emphasizes foreground-background differences. Compared with previous works, this paper achieves$1.28\times $improvements in the parameters and$1.32\times $faster inference speed than the original ResNet architecture.

In autonomous driving systems, the monocular 3D object detection algorithm is a crucial component. The safety of autonomous vehicles heavily depends on a well-designed detection system. Therefore, developing a robust and efficient 3D object detection algorithm is a major goal for institutes and researchers. Having a 3D sense is essential in autonomous vehicles and robotics, as it allows the system to understand its surroundings and react accordingly. Compared with stereo-based and Lidar-based methods, monocular 3D Object detection is a challenging task as it only utilizes 2D information to generate complex 3D features, making it low-cost, less computationally intensive, and with great potential. However, the performance of monocular methods is impaired due to the lack of depth information. In this paper, we propose a simple, end-to-end, and effective network for monocular 3D object detection without the use of external training data. Our work is inspired by auxiliary learning, in which we use a robust feature extractor as our backbone and multiple regression heads to learn auxiliary knowledge. These auxiliary regression heads will be discarded after training for improved inference efficiency, allowing us to take advantage of auxiliary learning and enabling the model to learn critical information more conceptually. The proposed method achieves 17.28% and 20.10% for the moderate level of the Car category on the KITTI benchmark test set and validation set, respectively, which outperforms the previous monocular 3D object detection approaches.

On-road object detection is a critical component in an autonomous driving system. The safety of the vehicle can only be as good as the reliability of the on-road object detection system. Thus, developing a fast and robust object detection algorithm has been the primary goal of many automotive industries and institutes. In recent years, multi-purpose vision-based driver assistance systems have gained popularity with the emergence of a deep neural network. A monocular camera has been developed to locate an object in the image plane and estimate the distance of the said object in the real world or the vehicle plane. In this work, we present a monocular 3D object detection method that utilizes the discrete depth and orientation representation. Our proposed method strives to predict object locations on 3D space utilizing keypoint detection on the object’s center point. To improve the point detection, we employ center regression on the objects segmentation mask, reducing the detection offset significantly. The simplicity of our proposed network architecture and its one-stage approach allows our algorithm to achieve competitive speed compared with prior methods. Our proposed method is able to achieve 26.93% detection score on the Cityscapes 3D object detection dataset, outperforming the preceding monocular method by a margin of 2.8 points.

An increasing number of tasks have been developed for autonomous driving and advanced driver assistance systems. However, this gives rise to the problem of incorporating plural functionalities to be ported into a power-constrained computing device. Therefore, the objective of this work is to alleviate the complex learning procedure of the pixel-wise approach for driving scene understanding. In this paper, we go beyond the pixel-wise detection of the semantic segmentation task as a point detection task and implement it to detect free space and lane. Instead of pixel-wise learning, we trained a single deep convolution neural network for point of interest detection in a grid-based level and followed with a computer vision (CV) based post-processing of end branches corresponding to the characteristic of target classes. To achieve the corresponding final result of pixel-wise detection of semantic segmentation and parametric description of lanes, we propose a CV-based post-processing to decode points of output from the neural network. The final results showed that the network could learn the spatial relationship for point of interest, including the representative points on the contour of the free space segmented region and the representative points along the center of the road lane. We verify our method on two publicly available datasets, which achieved 98.2% mIoU on the KITTI dataset for the evaluation of free space and 97.8% accuracy on the TuSimple dataset (with the field of view below the$y=320$axis) for the evaluation of the lane.

With better experience of immersive scene, the virtual reality (VR) becomes the main stream of entertainments. Featuring high chromatic displaying performance, relatively higher efficiency in power and lower latency, the Active-Matrix Organic Lighting-Emitting Diode (AMOLED) is the best-choice display technology for VR. However, AMOLED still requires the higher power consumption amongst other components on smart phones. Thus, various studies attempted to leverage the property of AMOLED to lower the power consumption while preserving the visual quality. This paper proposes a perceptually saliency-oriented transformation by incorporating the concept of how human eyes work in VR environment to provide more suitable experience while saving more power consumption. Experimental results show the proposed method preserves up to 49.33% of the power demand with high perceptual quality as other existing techniques. Furthermore, the subjective experiment demonstrates the proposed method provides a better perceptual quality for VR environment.

As an emissive display, the active matrix organic light-emitting diodes (AMOLEDs) endure lower power efficiency at the higher level of pixel intensities. In the existing techniques, the power consumption is lowered with a significant loss of details and hue alterations. This paper proposes a hue-preserving pixel-dimming technique using subtractive coefficients based on the decomposed hue-saturation-value color map that reduces the power consumption on AMOLED displays. An entropy-based scene detection is adopted to maintain the computational efficiency of the proposed method on video input. Experimental results on a 5.5-in 1080p AMOLED displays show that the proposed method conserves up to 73% of the displaying power with high perceptual qualities as compared with the existing methods.

This paper aims to present an algorithm that specifically enhances maxillary sinuses using a novel contrast enhancement technique based on the adaptive morphological texture analysis for occipitomental view radiographs. First, the skull X-ray (SXR) is decomposed into rotational blocks (RBs). Second, each RB is rotated into various directions and processed using morphological kernels to obtain the dark and bright features. Third, a gradient-based block segmentation decomposes the interpolated feature maps into feature blocks (FBs). Finally, the histograms of FBs are equalized and overlaid locally to the input SXR. The performance of the proposed method was evaluated on an independent dataset, which comprises of 145 occipitomental view-based human SXR images. According to the experimental results, the proposed method is able to increase the diagnosis accuracy by 83.45% compared with the computed tomography modality as the gold standard.

In 3D-IC architecture, vertically stacked multiple layer impedes heat dissipation and exacerbates thermal problem especially for reliability degradation. In this paper, we propose a cluster-based reliability- and thermal- aware 3D floorplanning to place modules. We derive a cost function considering both reliability and thermal factors with the balance among the chip of area, wire length, power density and density of STSV in the floorplan. Then we insert rectangle-STSVs and double-STSVs for improving reliability by modified Ford-Fulkerson method. Furthermore, we enhance redundant STSVs insertion rate by RSI algorithm. The experimental results show that more than 80% of single-STSVs can be replaced by rectangle-STSVs or double-STSVs, improving reliability accordingly. After STSV insertion, we construct a precise thermal conduction model to compute temperature distribution and insert TTSVs.Our framework is able to reduce the peak temperature effectively and maintain around 80 °C with minimal TTSVs based on a precise temperature computation model.

The performance of the sparse matrix-vector multiplication (SMVM) on a parallel system is strongly affected by the distribution of data among its components. Two costs arise as a result of the used data mapping method: arithmetic and communication. The communication cost often dominates the arithmetic cost, and the gap between these costs tends to increase. Therefore, finding a mapping method that reduces the communication cost is of high importance. On the other hand, the load distribution among the processing units must not be sacrificed. In this paper, a data mapping method is proposed for SMVM on Network-on-Chip which achieves balanced working load and reduces the communication cost. Afterwards, an FPGA-based architecture is introduced which is designed to fit with the proposed data mapping method.

In this paper, a power-saving method for emissive display by shrinking histogram is proposed. Based on a modern pixel-level power model of an OLED module, the power consumption factor can be employed in the objective function. Nevertheless, contrast enhancement intrinsically contradicts saving power. In order to solve this problem, we formulate a new objective function which is subject to the constant entropy. By minimizing the distance between two near non-empty bins of image histogram, the power reduction and entropy preservation are simultaneously achieved. To further enhance the perceptional quality, the proposed method is also integrated with other related algorithms. Experimental results show that the proposed method is capable of reducing display power, while the performance of contrast enhancement is also improved.

Despite the rapid advances in process technology, via failure is still problematic in nanometer-scale semiconductor manufacturing. Adding redundant vias is a typical approach for improving yield and reliability. Cell-based design methodologies are widely adopted in the industry for application-specific integrated circuits. Standard cells are effective for increasing the insertion rate of redundant via1s in cell-based designs. This study proposes an efficient library check and staggered pin arrangement approach that compares redundant via1 insertion rate in different configurations such as double-via and rectangle-via. To compare the variability in standard cell (SC) libraries, accurate characterization results are provided. Moreover, the proposed SC library is easily implemented in all currently available routers. The experimental results reveal that the proposed library improves total inserted redundant vias, total inserted redundant via1s, and total run time by 20.2%, 51.9%, and 42.3%, respectively. In double-via pattern, the proposed approach improves average via1 insertion rate by 14.6%. In rectangle-via pattern, the proposed approach achieves a 100% via1 insertion rate.

This paper proposes an efficient method for contrast enhancement using various inter-pixel contextual information. In order to make full use of the contextual and variational information, a two-dimensional (2D) histogram of the input image must be generated using mutual relationship between each pixel and the corresponding neighbourhoods, while the additional execution time is consumed due to the joint spatial and range filtering. In order to solve this problem, a constant time O(1) 2D target histogram (CTTH) method based on the characteristic of integral histogram is proposed to generate 2D histogram for contrast enhancement. Constant time means that the execution time of the joint spatial procedure remains same even if the mask size becomes very large. Experimental results demonstrate the efficiency of the proposed method by the arithmetic evaluation and a report of time consumption.

Automatic video surveillance is of critical importance to security in commercial, law enforcement, military, and many other environments due to terrorist activity and other social problems. Generally, motion detection plays an important role as the threshold function of background and moving objects in video surveillance systems. This paper proposes a novel motion detection method with a background model module and an object mask generation module. We propose a self-adaptive background matching method to select the background pixel at each frame with regard to background model generation. After generating the adaptive background model, the binary motion mask can be computed by the proposed object mask generation module that consists of the absolute difference estimation and the Cauchy distribution model. We analyze the detection quality of the proposed method based on qualitative visual inspection. On the other hand, quantitative accuracy measurement is also obtained by using four accuracy metrics, namely, Recall, Precision, Similarity, andF1. Experimental results demonstrate the effectiveness of the proposed method in providing a promising detection outcome and a low computational cost.

Despite the rapid advances in process technology, via failure is still problematic in nanometer-scale semiconductor manufacturing. Adding redundant vias is the typical approach for improving yield and reliability. Standard cells are essential for increasing the insertion rate of redundant via1s in cell-based designs. This study proposes an efficient library check and staggered pin arrangement approach that considers different configurations of redundant vias such as double-via and rectangle-via in order to increase redundant via1 insertion rate. Moreover, the proposed standard cell library is easily implemented in all currently available routers. The experimental results reveal that the proposed library improves total inserted redundant vias, total inserted redundant via1s, and total run time by 20.5%, 33.3%, and 44.8%, respectively. Compared to conventional approach, the average via1 insertion rate in double-via pattern is improved by 14.8%, and the via1 insertion rate in rectangle-via pattern is achieved at 100%.

This paper presents the architecture and implementation of a real-time adaptive Wiener filter for non-stationary noise cancellation in a car environment. The Wiener filter has been implemented in a Xilinx Virtex-5 chip and the target device is chosen as xc5vlx110t. The proposed design can filter each 32 samples within 918 micro seconds. The peak sampling rate is estimated to be 88.6KHz. The performance of proposed design is measured as 15.85dB noise reduction.

In this paper, we propose a novel background subtraction approach in order to accurately detect moving objects. Our method involves three important proposed modules: a block alarm module, a background modeling module, and an object extraction module. The block alarm module efficiently checks each block for the presence of either a moving object or background information. This is accomplished by using temporal differencing pixels of the Laplacian distribution model and allows the subsequent background modeling module to process only those blocks that were found to contain background pixels. Next, the background modeling module is employed in order to generate a high-quality adaptive background model using a unique two-stage training procedure and a novel mechanism for recognizing changes in illumination. As the final step of our process, the proposed object extraction module will compute the binary object detection mask through the applied suitable threshold value. This is accomplished by using our proposed threshold training procedure. The performance evaluation of our proposed method was analyzed by quantitative and qualitative evaluation. The overall results show that our proposed method attains a substantially higher degree of efficacy, outperforming other state-of-the-art methods bySimilarityandF1accuracy rates of up to 35.50% and 26.09%, respectively.

As the process technology advances, not only capacitive but also inductive effect is considered for bus encoding. However, most existing coding techniques only consider power or delay reduction based on either the RC or RLC model. This is due to the fact that the variation of power is hard to generalize together with noise and delay by using the RLC model. In this paper, we first show the growth and decline of power and noise behaviors while considering the RLC effect. According to the observations, we devise a quantitative cost function, which adopts the priority between capacitive and inductive effects on trade-off between power and noise. Based on the cost function, we then propose an invert-base bus encoding scheme to reduce power, noise, and delay simultaneously. Experimental results show that power, noise, and delay reductions by using our scheme are up to 19.97%, 14.73%, and 17.70% respectively for an 8-bit bus.

In this paper, we propose a novel background subtraction approach in order to accurately detect moving objects. Our method involves three important proposed modules: a block alarm module, a background modeling module, and an object extraction module. Our proposed block alarm module efficiently checks each block for the presence of either moving object or background information. This is accomplished by using temporal differencing pixels of the Laplacian distribution model and allows the subsequent background modeling module to process only those blocks found to contain background pixels. For our proposed background modeling module, a unique two-stage background training procedure is performed using Rough Training followed by Precise Training in order to generate a high-quality adaptive background model. As the final step of our process, we present an object extraction module which will compute the binary object detection mask through the applied suitable threshold value. This is accomplished by using our proposed threshold training procedure in order to achieve accurate and complete detection of moving objects. The overall results of these analyses demonstrate that our proposed method attains a substantially higher degree of efficacy, outperforming other state-of-the-art methods by Similarity and F1accuracy rates of up to 57.17% and 48.48%, respectively.

In order to implement watermarking scheme for embedded systems, we present an energy efficient and robust watermarking mechanism based on DS-CDMA. The DS-CDMA based watermarking can obtain the capacity according to the orthogonal spreading codes. The high capacity can improve the robustness efficiently. For power saving, we propose a low complexity frequency domain transform for the DS-CDMA embedding method. The experimental results show that our approach not only reduces 82.19% energy consumption, but can survive from various signal distortions such as JPEG compression, sharpening, blurring, intensity adjustment, and cropping.

Content addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in fast search time, it also significantly increases power consumption. In this paper, we propose a gate- block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based CAM (PB-CAM) to improve the efficiency for specific applications such as embedded systems. Through experimental results, we found that our approach effectively reduces the number of comparison operations for specific data types (ranging from 19.24% to 27.42%) compared with the 1's count approach. We used Synopsys Nanosim to estimate the power consumption in TSMC 0.35 um CMOS process. Compared to the 1's count PB-CAM, our proposed PB-CAM achieves 17.72% to 21.09% in power reduction for specific data types.

Document image binarization plays an important role in many applications such as optical character recognition, automatic bank check processing, and vehicle license recognition. This paper proposes an efficient binarization algorithm with intelligent block size detection. Based on the image characteristic, the document image is automatically divided into several blocks with various sizes. Then, a threshold surface is constructed to derive the binary image. Experimental results show that the proposed method not only provide promising binarization result, but also low computational cost.

Content-addressable memory (CAM) is frequently used in applications, such as lookup tables, databases, associative computing, and networking, that require high-speed searches due to its ability to improve application performance by using parallel comparison to reduce search time. Although the use of parallel comparison results in reduced search time, it also significantly increases power consumption. In this paper, we propose a Block-xor approach to improve the efficiency of low power precomputation-based CAM (PB-CAM). Through mathematical analysis, we found that our approach can effectively reduce the number of comparison operations by 50% on average as compared with the ones-count approach for 32-bit-long inputs. In our experiment, we used Synopsys Nanosim to estimate the power consumption in TSMC 0.35-mum CMOS technology. Compared with the ones-count PB-CAM system, the experimental results show that our proposed approach can achieve on average 30% in power reduction and 32% in power performance reduction. The major contribution of this paper is that it presents theoretical and practical proofs to verify that our proposed Block-xor PB-CAM system can achieve greater power reduction without the need for a special CAM cell design. This implies that our approach is more flexible and adaptive for general designs.

Content addressable memory (CAM) is widely used in many applications that require fast table lookup. Due to the parallel comparison feature and high frequency of lookup, however, the power consumption of CAM is usually significant. In this paper we propose a decoupled match line scheme which combines the performance advantage of the traditional NOR-type CAM and the power efficiency of the traditional NAND-type CAM. In our design, a CAM word is divided into two segments, and then all the CAM cells are decoupled from the match line. By minimizing both the match line capacitances and switching activities, our design can largely reduce the CAM power dissipated in search operations. The results measured from the fabricated chip show that without any performance penalty our design can reduce the search energy consumption of the CAM by 89% compared to the traditional NOR-type CAM design

Human face detection plays an important role in many applications such as video surveillance, face recognition, and face image database management. This paper describes a fast face detection algorithm with accurate results. We use lighting compensation to improve the performance of color-based scheme, and reduce the computation complexity of feature-based scheme. Our method is effective on facial variations such as dark/bright vision, close eyes, open mouth, a half-profile face, and pseudo faces. It is worth stressing that our algorithm can also discriminate cartoon and human face correctly. The experimental results show that our approach can detect a frame in 111 msecs with the 92.3% detection rate

In this paper, we propose a method to solve the multiple supply voltage scheduling problem which is to assign the operational nodes of a control/data flow graph to a voltage level to minimize the average power consumption within a given computation time. Different from the previous researches focused on the operational nodes in the critical path and utilized the slack time to change the voltage of other nodes, our method can deal with all nodes without considering whether the node is in the critical path or not, and the benefit is that the voltage assignment of each node becomes more flexible. The proposed method consists of two phases, the scheduling phase and the adjusting phase, and considers both the power (delay) of the computational components and the power (delay) of the level shifters. Experimental result shows that using three voltages on a number of standard benchmarks, an average power saving of 34.23% can be obtained if the delay overhead is set as 0, and 48.07% can be obtained if the total delay is set as 1.6 times of the original delay.

As technology scales down to nanometer dimensions, coupling capacitances between adjacent bus wires grow rapidly, and have a significant impact on power consumption and signal integrity of an integrated circuit. As buses are major components of a design, it is important to design fault-tolerant buses that dissipate less power and raise reliability without sacrificing performance. In this paper, we address the problem of using Hamming single error correcting code by optimizing both wire permutation and spacing. We propose an efficient polynomial time algorithm which applies graph theory for this optimization problem. Unlike previous studies [17], our approach can be applied to high bandwidth fault-tolerant buses to efficiently reduce the coupling capacitances by utilizing available space. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs for evaluating energy reduction. The results show that our approach can save energy up t o 43% for the best case, and 30% for the worst with 20 × dmin (d min is the mininal permitted wire distance) additional width on RLC model. Besides, we also provided comprehensive comparisons in experimental result section for different fault-tolerant bus layout methods and error correction codes.

The use of deep-submicrometer (DSM) technology increases the capacitive coupling between adjacent wires leading to severe crosstalk noise, which causes power dissipation and may also lead to malfunction of a chip. In this paper, we present a technique that reduces crosstalk noise on instruction buses. While previous research focuses primarily on address buses, little work can be applied efficiently to instruction buses. This is due to the complex transition behavior of instruction streams. Based on instruction sequence profiling, we exploit an architecture that encodes pairs of bus wires and permute them in order to optimize power and noise. A close to optimal architecture configuration is obtained using a genetic algorithm. Unlike previous bus encoding approaches, crosstalk reduction can be balanced with delay and area overhead. Moreover, if delay (or area) is most critical, our architecture can be tailored to add nearly no overhead to the design. For our experiments, we used instruction bus traces obtained from 12 SPEC2000 benchmark programs. The results show that our approach can reduce crosstalk up to 50.79% and power consumption up to 55% on instruction buses.

In this article, we present a bipartition dual-encoding architecture for low-power pipelined circuits. We exploit the bipartition approach as well as encoding techniques to reduce power dissipation not only of combinational logic blocks but also of the pipeline registers. Based on Shannon expansion, we partition a given circuit into two subcircuits such that the number of different outputs of both subcircuits are reduced, and then encode the output of both subcircuits to minimize the Hamming distance for transitions with a high switching probability. We measure the benefits of four different combinational bipartitioning and encoding architectures for comparison. The transistor-level simulation results show that bipartition dual-encoding can effectively reduce power by 72.7% for the pipeline registers and 27.1% for the total power consumption on average. To the best of our knowledge, it is the first work that presents an in-depth study on bipartition and encoding techniques to optimize power for pipelined circuits.

The waveform data, which is gathered during digital simulation of large and complex systems easily fill up huge amounts of disk space on the simulation computer. This is specially true for many deep-submicron designs. Hence, we developed a set of algorithms and techniques which can be used to efficiently compress digital waveforms without losing any significant information from the original data. Experimental results show that compression ratios of up to 300 compared to a original VCD formatted file can be achieved.

Power consumption is an increasingly pressing problem in modern processor design. Since the on-chip caches usually consume a significant amount of power, it is one of the most attractive targets for power reduction. This paper presents a two-level filter scheme, which consists of the L1 and L2 filters, to reduce the power consumption of the on-chip cache. The main idea of the proposed scheme is motivated by the substantial unnecessary activities in conventional cache architecture. We use a single block buffer as the L1 filter to eliminate the unnecessary cache accesses. In the L2 filter, we then propose a new sentry-tag architecture to further filter out the unnecessary way activities in case of the L1 filter miss. We use SimpleScalar to simulate the SPEC2000 benchmarks and perform the HSPICE simulations to evaluate the proposed architecture. Experimental results show that the two-level filter scheme can effectively reduce the cache power consumption by eliminating most unnecessary cache activities, while the compromise of system performance is negligible. Compared to a conventional instruction cache (32 kB, two-way) implemented with only the L1 filter, the use of a two-level filter can result in roughly 30% reduction in total cache power consumption. Similarly, compared to a conventional data cache (32 kB, four-way) implemented with only the L1 filter, the total cache power reduction is approximately 46%.

For physical caches, the address translation delay can be partially masked, but it is hard to avoid completely. In this paper, we propose a cache partition architecture, called paged cache, which not only masks the address translation delay completely but also reduces the tag area dramatically. In the paged cache, we divide the entire cache into a set of partitions, and each partition is dedicated to only one page cached in the TLB. By restricting the range in which the cached block can be placed, we can eliminate the total or partial tag depending on the partition size. In addition, because the paged cache can be accessed without waiting for the generation of physical address, i.e., the paged cache and the TLB are accessed in parallel, the extended cache access time can be reduced significantly. We use SimpleScalar to simulate SPEC2000 benchmarks and perform HSPICE simulations (with a 0.18 /spl mu/m technology and 1.8 V voltage supply) to evaluate the proposed architecture. Experimental results show that the paged cache is very effective in reducing tag area of the on-chip Ll caches, while the average extended cache access time can be improved dramatically.

In this paper we propose a bipartition dual-encoding architecture for low power pipelined circuit. Pipelined circuits consist of combinational logic blocks separated by registers which usually consume a large amount of power Although the clock gated technique is a promising approach to reduce switching activities of the pipelined registers, this approach is restricted by the placement of the registers and the additional control signals that must be generated. Thus, we propose a technique for optimizing power dissipation of a pipelined circuit addressing registers and combinational logic blocks at the same time. Our approach modifies the registers using bipartition and encoding techniques. In our experiments power consumption were reduced by 72.9% for pipelined registers and 30.4% for the total pipelined stage on average.

This work proposes a new algorithm to synthesize low power bipartition-codec architecture for pipelined circuits. The bipartition-codec architecture has been introduced as an effective power reduction technique for circuit design. The entropy-based partition-codec (ENPCO) algorithm extends this approach as it optimizes for both: power and area. It uses entropy as a criterion to balance between power and area. The ENPCO algorithm is composed of two phases: first, it clusters the output vectors with high occurrence into a group, moving all remaining output vectors into another group. The first group will be encoded in order to save power. Secondly, based on circuit entropy, output patterns are moved between both groups in order to balance power consumption and area overhead. A number of Microelectronic Center of North Carolina (MCNC) benchmarks were used to verify the effectiveness of our algorithm. Results demonstrate that ENPCO algorithm can achieve low power with less area overhead than the single-phase algorithm introduced previously by Shanq-Jang Ruan et al. (1999).

This paper proposes a new approach to synthesize pipelined circuits with low-power consideration. We treat each output value of a combinational circuit as one state of a finite-state machine (FSM). If the output of a combinational circuit transits mainly among some few states, we could extract those states (output) and the corresponding input to build a subcircuit. After bipartitioning the circuit, we apply the encoding technique to the highly active subcircuit for further power reduction. In this paper, we formulate the bipartition problem and present a probabilistic-driven algorithm to bipartition a circuit so as to minimize the power dissipation. Our experimental results show that an average power reduction on several Microelectronic Center of North Carolina (MCNC) benchmarks of 31.6% is achievable.

Multicasting has been widely utilized for delivering messages from one sender to multiple recipients. Nowadays in some applications such as pay per view or video-conferencing systems, the messages delivered via multicasting should be available to authorized recipients only. Therefore, secure multicasting becomes an important design issue in a distributed environment. To achieve secure multicasting, all authorized recipients form a group and share a group key; messages should be encrypted by the key before they are multicasted. For the sake of security, we need a new group key if someone joins/leaves the group. Consequently, our goal is aimed at finding a way to distribute the new key securely and efficiently. We propose a new solution to the problem; we distribute new keys through a special function called the secure filter. Compared with related work, our solution requires less system resources to change group members.

Proposes a new bipartition-codec architecture that may reduce the power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of a finite-state machine. If the output of a pipelined circuit mainly transitions among just a few states, we can partition the combinational portion of a pipelined circuit into two blocks: the one that contains the few states of high activity is small, and the other (that contains the remainder of low activity) is large. Consequently, the state transitions are confined to the small block most of the time. Then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. The encoder minimizes the number of bit changes during state transitions; thus, the switching which propagates into the decoder is reduced considerably. We present experimental results on several MCNC benchmarks and obtain power savings of up to 63.7% by using our new architecture.