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Takashi Hagiwara

dblp:67/1039 · DBLP profile ↗
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4ranked-venue papers
0as first author
0since 2021 · last 2007
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3Computer networks · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
High-performance computing · 85% Parallel and multicore computing · 9% Electronic design automation · 5%

Topics — the 7 heaviest of 7, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
High-performance computing › scientific computing systems
atmospheric modeling
0.012002
A 26.58 Tflops global atmospheric simulation with the spectral transform method on the Earth Simulator · SC 2002
High-performance computing
scientific computing systems
0.012002
A 26.58 Tflops global atmospheric simulation with the spectral transform method on the Earth Simulator · SC 2002
High-performance computing › supercomputer architecture
vector supercomputer
0.012002
A 26.58 Tflops global atmospheric simulation with the spectral transform method on the Earth Simulator · SC 2002
Parallel and multicore computing
dataflow computing
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989
Electronic design automation › high-level synthesis › scheduling
dataflow graph scheduling
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989
Parallel and multicore computing
parallel program transformation
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989
Performance modeling and evaluation › simulation
simulation-based evaluation
0.011989
A preceding activation scheme with graph unfolding for the parallel processing system-array · SC 1989

Methods — techniques the papers use, named apart from their topics

spectral transform method · 0.0graph unfolding · 0.0dataflow graph construction · 0.0
YearPublicationVenuePosition
2007 Linear Precoding with Minimum BER Criterion for MIMO-OFDM Systems Employing ML Detection
abstract
This paper proposes a new MIMO-OFDM preceding method that minimizes BER of the maximum likelihood detection (MLD). Conventional MIMO precoding methods can approximately minimize BER of the minimum mean square error (MMSE) based detector by using singular value decomposition (SVD) of the channel matrices. However, they cannot minimize BER of MLD because the orthogonalization does not increase the Euclidean distance between a pair of channel-distorted replicas of transmitted signals. To optimize the Euclidean distance effectively, the proposed method controls its precoding parameters by minimizing the upper bound of BER based on the pairwise error. Computer simulations demonstrate that the proposed precoding method outperforms the MMSE precoder and the conventional minimum BER (MBER) precoder that assumes the precoding matrix structure similar to the solution of the weighted MMSE precoder.
Boonsarn Pitakdumrongkija, Kazuhiko Fukawa, Hiroshi Suzuki, Takashi Hagiwara
ICC4
2002 A 26.58 Tflops global atmospheric simulation with the spectral transform method on the Earth Simulator
abstract
A spectral atmospheric general circulation model called AFES (AGCM for Earth Simulator) was developed and optimized for the architecture of the Earth Simulator (ES). The ES is a massively parallel vector supercomputer that consists of 640 processor nodes interconnected by a single stage crossbar network with its total peak performance of 40.96 Tflops was achieved for a high resolution simulation (T1279L96) with AFES by utilizing the full 640-node configuration of the ES. The resulting computing efficiency is 64.9% of the peak performance, well surpassing that of conventional weather/climate applications having just 25-50% efficiency even on vector parallel computers. This remarkable performance proves the effectiveness of the ES as a viable means for practical applications.
Satoru Shingu, Hiroshi Takahara, Hiromitsu Fuchigami, Masayuki Yamada, Yoshinori Tsuda, Wataru Ohfuchi, Yuji Sasaki, Kazuo Kobayashi, Takashi Hagiwara, Shinichi Habata, Mitsuo Yokokawa, Hiroyuki Itoh, Kiyoshi Otsuka
SC9
1989 A preceding activation scheme with graph unfolding for the parallel processing system-array
abstract
The purpose of this paper is to propose and evaluate a new scheme, called the Preceding Activation Scheme with Graph Unfolding, which translates a FORTRAN program into a dataflow graph and executes it efficiently. The problems in restructuring a FORTRAN program into a dataflow graph are that (1) a FORTRAN program is not written in a single assignment rule and (2) it has an explicit control flow. These problems result in little parallelism because many gate-operations, such as T/F gates, are introduced in the dataflow graph to synchronize the data movement. Therefore, discarding these gate-operations is the key to exposing parallelism in a FORTRAN program. In this paper, the preceding activation scheme with graph unfolding is proposed to discard these gate-operations. Then, the result of the performance evaluation by the -Harray- software simulator is presented. It is shown that the execution speed with the proposed scheme for flow graphs without backward branches is about 1.5 times as fast as that with the extended activation scheme which initiates the execution only after it is confirmed that a basic block will be selected at a conditional branch. Moreover, the execution speed is 2.7 times as fast as that with the extended activation scheme if a flow graph including backward branches are unfolded by the proposed scheme.
Hayato Yamana, Takashi Hagiwara, Jun Kohdate, Yoichi Muraoka
SC2
1988 System architecture of parallel processing system -Harry-
abstract
This paper proposes a parallel processing system -Harray- for scientific computations. Data flow computers are expected to obtain the high performance because they can extract parallelism fully from a program. However, they have many problems, such as the difficulty of controlling the sequence of execution. The -Harray- system is an array processor which adapts two levels of control mechanism; data flow execution in each processor and control flow between processors, in order to take full advantage of both mechanisms. A task which is assigned to a processor is called a “macro-block”. Three types of macro-blocking and three types of activation schemes for the macro-block which initiates its execution are introduced in order to attain the high performance. Moreover, a hardware synchronization mechanism is used to reduce synchronization overhead and to gain the liner speedup of the -Harray- system.
Hayato Yamana, Toshikazu Marushima, Takashi Hagiwara, Yoichi Muraoka
ICS3