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Karja Danuwidjaja

dblp:67/107 · DBLP profile ↗
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1ranked-venue papers
0as first author
0since 2021 · last 1987
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Hardware accelerators and domain-specific architectures · 87% Electronic design automation · 13%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures › scientific computing accelerator
circuit simulation acceleration
0.011987
A Vector Hardware Accelerator with Circuit Simulation Emphasis · DAC 1987
Hardware accelerators and domain-specific architectures › data-parallel accelerator
vector accelerator
0.011987
A Vector Hardware Accelerator with Circuit Simulation Emphasis · DAC 1987
Electronic design automation
circuit simulation
0.011987
A Vector Hardware Accelerator with Circuit Simulation Emphasis · DAC 1987

Methods — techniques the papers use, named apart from their topics

pipelined floating-point processing · 0.0SIMD architecture · 0.0
YearPublicationVenuePosition
1987 A Vector Hardware Accelerator with Circuit Simulation Emphasis
abstract
A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650.
Andrei Vladimirescu, Manolis Katevenis, Zvika Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, Niraj Jain, Steven Lass
DAC6