Demo Data from EDBT 2026 / reviewers in the wild / expert
Robert C. Dorr
dblp:67/10979
· DBLP profile ↗
2ranked-venue papers
1as first author
0since 2021 · last 1973
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Hardware reliability and fault tolerance · 46% Processor architecture and microarchitecture · 25% Integrated circuit design · 22% |
Topics — the 4 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Integrated circuit design
digital circuit design |
0.0 | 1 | 1972 | Self-Checking Combinational Logic Binary Counters · IEEE Trans. Computers 1972 |
Processor architecture and microarchitecture › microprogramming
microprogrammable processor |
0.0 | 1 | 1973 | The Design of a Microprogrammed Self-Checking Processor of an Electronic Switching System · IEEE Trans. Computers 1973 |
Hardware reliability and fault tolerance
self-checking circuits |
0.0 | 1 | 1972 | Self-Checking Combinational Logic Binary Counters · IEEE Trans. Computers 1972 |
Embedded and real-time systems
electronic switching system |
0.0 | 1 | 1973 | The Design of a Microprogrammed Self-Checking Processor of an Electronic Switching System · IEEE Trans. Computers 1973 |
Methods — techniques the papers use, named apart from their topics
parity prediction · 0.0microprogramming · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1973 | The Design of a Microprogrammed Self-Checking Processor of an Electronic Switching SystemabstractThis paper describes the internal workings of a low-cost microprogrammed processor designed to control electronic switching systems. The machine is structurally regular to ease maintenance difficulties and allow more efficient packaging. Herbert Y. Chang, Robert C. Dorr, Daniel J. Senese |
IEEE Trans. Computers | 2 |
| 1972 | Self-Checking Combinational Logic Binary CountersabstractA high-speed, self-checking count circuit realization is attainable by using combinational logic and parity prediction. The utilization of combinational logic as opposed to sequential logic design generally minimizes the amount of software necessary for routine and diagnostic testing. Count circuits with parity prediction find application in stand-alone, self-checking processors. Robert C. Dorr |
IEEE Trans. Computers | 1 |