EDBT 2026 Demo / reviewers in the wild / expert
Cedomir Segulja
dblp:67/11097
· DBLP profile ↗
3ranked-venue papers
3as first author
0since 2021 · last 2015
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3 · 3 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Software engineering, system software, and programming languages
1 paper |
Concurrent programming · 100% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Storage systems · 77% Processor architecture and microarchitecture · 23% |
Topics — the 3 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Concurrent programming › concurrency bug detection
data race detection |
0.2 | 1 | 2015 | Clean: a race detector with cleaner semantics · ISCA 2015 |
Storage systems › file systems
versioning |
0.1 | 1 | 2012 | Architectural support for synchronization-free deterministic parallel programming · HPCA 2012 |
Concurrent programming
memory models |
0.1 | 1 | 2015 | Clean: a race detector with cleaner semantics · ISCA 2015 |
Methods — techniques the papers use, named apart from their topics
FPGA prototype · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2015 | Clean: a race detector with cleaner semanticsabstractData races make parallel programs hard to understand. Precise race detection that stops an execution on first occurrence of a race addresses this problem, but it comes with significant overhead. In this work, we exploit the insight that precisely detecting only write-after-write (WAW) and read-after-write (RAW) races suffices to provide cleaner semantics for racy programs. We demonstrate that stopping an execution only when these races occur ensures that synchronization-free-regions appear to be executed in isolation and that their writes appear atomic. Additionally, the undetected racy executions can be given certain deterministic guarantees with efficient mechanisms. Cedomir Segulja, Tarek S. Abdelrahman |
ISCA | 1 |
| 2014 | What is the cost of weak determinism?abstractWe analyze the fundamental performance impact of enforcing a fixed order of synchronization operations to achieve weak deterministic execution. Our analysis is in three parts, performed on a real system using the SPLASH-2 and PARSEC benchmarks. First, we quantify the impact of various sources of non-determinism on execution of data-race-free programs. We find that thread synchronization is the prevalent source of non-determinism, sometimes affecting program output. Second, we divorce the implementation overhead of a system imposing a specific synchronization order from the impact of enforcing this order. We show that this fundamental cost of determinism is small (slowdown of 4% on average and 32% in the worst case) and we identify application characteristics responsible for this cost. Finally, we evaluate this cost under perturbed execution conditions. We find that demanding determinism when threads face such conditions can cause almost 2x slowdown. Cedomir Segulja, Tarek S. Abdelrahman |
PACT | 1 |
| 2012 | Architectural support for synchronization-free deterministic parallel programmingabstractWe propose a novel synchronization mechanism called versioning. It dynamically establishes a deterministic order of memory accesses in parallel programs that have serial semantics, in a way that is transparent to the programmer. This order is created in a distributed manner and is enforced by monitoring memory accesses and stalling threads if necessary. Versioning gives rise to parallel programming models in which programmers need not explicitly synchronize threads and only need to specify shared data, which greatly simplifies parallel programming. However, versioning introduces overheads and thus demands architectural support. We describe versioning and the architectural support it needs. We also propose one parallel programming model that utilizes versioning and use it to parallelize 13 benchmark applications. We build an FPGA prototype of a multiprocessor system with versioning support and show that good parallel speedups are obtained. Our analysis shows minimal impact of versioning, both in terms of timing overheads and in terms of additional hardware. Cedomir Segulja, Tarek S. Abdelrahman |
HPCA | 1 |