Demo Data from EDBT 2026 / reviewers in the wild / expert
Brian McMurtrey
dblp:67/1196
· DBLP profile ↗
3ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 3
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 82% Performance modeling and evaluation · 18% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › design automation tools › FPGA CAD
FPGA design tools |
0.1 | 2 | 2003 | Web-based IP evaluation and distribution using applets · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 IP delivery for FPGAs using Applets and JHDL · DAC 2002 |
Electronic design automation
hardware verification and test |
0.0 | 1 | 2003 | Web-based IP evaluation and distribution using applets · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 2003 | Web-based IP evaluation and distribution using applets · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 |
Electronic design automation
circuit simulation |
0.0 | 1 | 2002 | IP delivery for FPGAs using Applets and JHDL · DAC 2002 |
Electronic design automation › logic synthesis › digital system synthesis
netlist generation |
0.0 | 1 | 2002 | IP delivery for FPGAs using Applets and JHDL · DAC 2002 |
Methods — techniques the papers use, named apart from their topics
java applets · 0.1JHDL · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2003 | Web-based IP evaluation and distribution using appletsabstractThis paper introduces an IP evaluation and delivery framework that operates within Java applets. The use of such applets allows circuit designers to create, evaluate, test, and obtain FPGA circuits directly within a Web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. An important component of this framework is the ability to deliver black-box simulation models as executable Java applets. These applet-based simulation models can be tied to third-party simulation tools using network sockets. Several techniques for interfacing black-box applet models to external simulators are described. Michael J. Wirthlin, Brian McMurtrey |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |
| 2002 | IP delivery for FPGAs using Applets and JHDLabstractThis paper introduces an FPGA IP evaluation and delivery system that operates within Java applets. The use of such applets allows designers to create, evaluate, test, and obtain FPGA circuits directly within a web browser. Based on the JHDL design tool, these applets allow structural viewing, circuit simulation, and netlist generation of application-specific circuits. Applets can be customized to provide varying levels of IP visibility and functionality as needed by both customer and vendor. Michael J. Wirthlin, Brian McMurtrey |
DAC | 2 |
| 2001 | Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures
Michael J. Wirthlin, Brian McMurtrey |
FPL | 2 |