MOTIVATION: Morphological and genetic spatial data from functional experiments based on genetic, surgical and pharmacological perturbations are being produced at an extraordinary pace in developmental and regenerative biology. However, our ability to extract knowledge from these large datasets are hindered due to the lack of formalization methods and tools able to unambiguously describe, centralize and interpret them. Formalizing spatial phenotypes and gene expression patterns is especially challenging in organisms with highly variable morphologies such as planarian worms, which due to their extraordinary regenerative capability can experimentally result in phenotypes with almost any combination of body regions or parts. RESULTS: Here, we present a computational methodology and mathematical formalism to encode and curate the morphological outcomes and gene expression patterns in planaria. Worm morphologies are encoded with mathematical graphs based on anatomical ontology terms to automatically generate reference morphologies. Gene expression patterns are registered to these standard reference morphologies, which can then be annotated automatically with anatomical ontology terms by analyzing the spatial expression patterns and their textual descriptions. This methodology enables the curation and annotation of complex experimental morphologies together with their gene expression patterns in a centralized standardized dataset, paving the way for the extraction of knowledge and reverse-engineering of the much sought-after mechanistic models in planaria and other regenerative organisms. AVAILABILITY AND IMPLEMENTATION: We implemented this methodology in a user-friendly graphical software tool, PlanGexQ, freely available together with the data in the manuscript at https://lobolab.umbc.edu/plangexq. SUPPLEMENTARY INFORMATION: Supplementary data are available at Bioinformatics online.

Current discrete event simulator requires heavy simulation overhead to switch between different components to simulate them in strictly chronological order. Therefore, timed simulation is significantly slower than un-timed simulation. By simply adding delays in the components and communication channels, our timed MPEG-2 decoder simulates more than 14 times slower than an un-timed simulation. In this paper, we propose a partial order method to speed up timed simulation by relaxing the order that the components are simulated. With partial order method, a component is not required to schedule a channel access if both behavioral and timing results of the access are known. The simulation switches less frequently hence the simulation overhead reduces. We show that partial order method can be used in complex system-level simulation such as MPSoC implementations of the MPEG-2 decoder. In our experiments, partial order method provides more than 10 times speedups over regular discrete event simulation for timed simulation.

Performance simulation of software for multiprocessor system-on-a-chips (MPSoC) suffers from poor tool support. Cycle accurate simulation at Instruction Set Simulation level is too slow and inefficient for any design of realistic size. Behavioral simulation, though useful for functional analysis at high level, does not provide any performance information that is crucial for design and analysis of MPSoC implementations. As a consequence, designers are often reduced to manually annotate performance information onto behavioral models, which contributes further to inefficiency and inaccuracy. In this paper, we use structural performance models to provide fast and accurate simulation of software for MPSoC.We generate structural models automatically using GCC with accurate performance annotation while considering optimizations for instruction selection, branch prediction, and pipeline interlock. Our structural models are able to simulate at several orders of magnitude faster than ISS and provide less than 1% error on performance estimation. These models allow realistic MPSoC design space explorations based on performance characteristics with simulation speed comparable to behavioral simulation. We validate our simulation models with several benchmarks and demonstrate our approach with a design case study of an MPEG-2 decoder.

Design of Multiprocessor System-on-a-Chips requires efficient and accurate simulation of every component. Since thememory subsystemaccounts for up to 50%of the performance and energy expenditures, it has to be considered in systemlevel design space exploration. In this paper, we present a novel technique to simulate memory accesses in software TLM/T models. We use a compiler to automatically expose all memory accesses in software and annotate them onto efficient TLM/T models. A reverse address map provides target memory addresses for accurate cache and memory simulation. Simulating at more than 10 MHz, our models allow realistic architectural design space explorations on memory subsystems. We demonstrate our approach with a design exploration case study of an industrial-strength MPEG-2 decoder.

In many IP media services, the media channels are point-to-point, dynamic, and set up with the participation of one or more application servers, even thou the media packets themselves travel directly between media endpoints. The application servers must be programmed so that media behavior is globally correct, even though the servers may attempt to manipulate the same media channels concurrently and without knowledge of each other. Our proposed solution to this problem of compositional media control includes an architecture-independent descriptive model, a set of high-level programming primitives, a formal specification of their compositional semantics, a signaling protocol, an implementation, and partial verification of correctness. The paper includes performance analysis, comparison to related work, and principles for making other networked applications more compositional.

The SIP servlet standard offers a familiar Java application programming interface (API) for developing session initiation protocol (SIP) applications, and the upcoming version 1.1 specification standardizes how multiple SIP servlet applications are composed and invoked to service a communication episode. Such disciplined composition promotes software modularity and reuse, and also helps manage feature interactions. At the core of the application composition framework in the SIP servlet API 1.1 is the Application Router that performs the task of selecting an application to service a SIP request. In this paper, the authors describe an application router implementation based on the distributed feature composition (DFC) architecture routing algorithm (DFC-AR). While the DFC-AR is designed to be simple so it can serve as a sample implementation, it is also sufficiently powerful for real-world VoIP service deployments. The DFC-AR has been proposed to be the default AR in the reference implementation of the 1.1 specification.

The SIP servlet standard is a popular Java application programming interface (API) for developing and deploying session initiation protocol (SIP) applications in Voice over IP (VoIP) environments. A number of commercial container implementations conforming to the current 1.0 specification are available; they provide feature rich and robust environments where a wealth of SIP applications can provide flexible control logic for advanced telecommunications applications. However, while one of the stated goals of the SIP servlet API is to support application composition, it is optional and not standardized in the 1.0 specification. In this paper, the authors propose an application composition framework that is general, powerful, and yet shields developers of individual applications from the complexities of application composition and feature interaction. Such a framework promotes modularity and application reuse. Also presented here are the results of implementing this framework on top of 1.0 implementations. This framework is being standardized for the new 1.1 SIP Servlet specification as part of the JCP JSR 289 process.

When there is more than one application server in the signaling path between IP media endpoints, and the servers manipulate media flow, media flow must be controlled com-positionally. This paper presents a protocol, signaling architecture, API, and API implementation for distributed, compositional media control. The semantics of the API is specified in linear temporal logic, and the implementation has been partially verified by model checking. The principles developed to solve this problem may be useful for making other network applications compositional.

An open (in the sense of extensible and programmable) architecture for IP telecommunications must be based on a comprehensive strategy for managing feature interaction. We describe our experience with BoxOS, an IP telecommunication platform that implements the DFC technology for feature composition. We present solutions to problems, common to all efforts in IP telecommunications, of feature distribution, interoperability, and media management. We also explain how BoxOS addresses many deficiencies in SIP, including how BoxOS can be used as a SIP application server.

Previous work in distributed feature composition architecture has shown that a modular, compositional architecture of feature logic can lead to successful management of feature interaction. It can also promote rapid deployment of new services and third party innovation in a communication network. ECLIPSE is an implementation of DFC that focuses on voice over IP (VoIP) and multimedia over IP. In ECLIPSE, the signaling messages traverse units of feature logic (feature boxes), but by necessity the media data have to take a separate and more direct path. This paper describes a scheme in which the feature boxes can cooperatively control the flow of media in an optimal path, while still maintaining the benefits of the DFC architecture. This scheme supports any desired media connectivity, and is independent of VoIP protocols (e.g. SIP and H.323), or the underlying media switch fabric implementation. This result is also applicable to other component architectures for communications. Comparison is made with other schemes proposed in the literature.