According to the growth of the Internet, an IP (Internet protocol) router with capacity of terabit/s is required in the near future. To achieve high capacity, the switch fabric should handle many pairs of input ports and output ports. For this purpose, a multistage network switch is required. This paper presents a new scalable multistage packet switch using deflection routing and shortest path routing multistage network. Deflection routing multistage networks have the advantage of hardware simplicity since the switch element has no buffer memory, and variable length packet switching can be easily handled. Furthermore, in the proposed new interconnection method between switch elements, the required amount of hardware is reduced compared with the conventional switch based on the deflection routing principle. A circuit of 8 /spl times/ 8 variable length packet switch element is designed on FPGA, and the required amount of hardware to realize a 64 /spl times/ 64 multistage network is calculated. It is shown that the 64 /spl times/ 64 switch will be implemented within one LSI chip, and that a 10 Tbit/s switch is realized by two-stage interconnection of the LSI chips.

The single-hop communication method of the current wireless network cannot meet new demands in the domain such as intelligent transport systems (ITS) and Home LAN. Even though the ad-hoc network architecture is expected to solve this problem, the nature of a dynamic topology makes this routing hard to realize. This paper introduces a new ad-hoc routing algorithm, which is inspired by the cooperating mobile agents for dynamic network routing of Miner et al. (see Software agents for future communicating systems, p.287-304, Springer, 1999). In their system, some control agents explore the network and update routing tables on their own knowledge. Using these routing tables, other agents deliver messages. They considered the feasibility of the agent-based routing system, but did not refer to an efficient algorithm. We consider that algorithm without increasing the network load. We propose multiplying each entry in the routing table to store much more information from agents and evaluating them to make better use of information, which succeeded in raising the network connectivity by about 40% by simulation.

Eventhough conventional multistage switch architecture such as a Banyan switch can support a high speed capacity, but it still has a high latency and is not scalable. Moreover under non-uniform traffic, blocking occurs. Therefore, a new switch architecture based on multi-dimensional crossbar (MDXB) switch is introduced, as a better solution. The MDXB switch is an interconnection among crossbar switches into multi-dimension network. We also propose a new node configuration and routing algorithm used in the MDXB switch to achieve even lower packet loss rate. The simulation results shown that MDXB switch achieves much higher throughput under a non-uniform traffic pattern.

We first present a mathematical model to evaluate the effect of traffic integration of broadband and narrowband services for a multimedia mobile communication system. The mathematical model gives the blocking probability for the dynamic channel assignment (DCA) scheme with both the carrier partitioning (CP) method and the carrier sharing (CS) method assuming a multi-carrier TDMA mobile communication environment. The proposed evaluation method is effective to analyze the characteristics of traffic integration, and shows that the CS method has a better performance compared with the CP method. The problem of the CS method is that narrowband traffic may cause blocking of the broadband traffic when there are a large number of channel fractions. To reduce this effect, we next propose a dynamic channel assignment algorithm based on the self adaptive channel allocation strategy which is named the reserved channel scheme. It reserves communication channels for broadband traffic by means of the frequency hopping technique to reduce the number of channel fractions. Simulation results show that the reserved channel strategy has better performance compared with the ARP (autonomous reuse partitioning) strategy.

To realize functionally distributed computing in a wide area distributed environment, distributed shared memory (DSM) is an attractive option due to the simplicity and flexibility in software programming. DSM has mainly been studied in a local environment. In a widely distributed environment, the latency of communication impacts system performance, even if a high bandwidth network is used. DSM models in a widely distributed environment are discussed and evaluated in this paper. First, two existing DSM models are examined: shared virtual memory and replicated shared memory. Next, an innovative replicated shared memory model, which uses internal machine memory, is proposed. A prototype of this model using multi-thread programming was implemented on multi-CPU SPARCstations. These DSM models are compared with SCRAMNet, whose mechanism is based on replicated shared memory. Results from this evaluation show the superiority of the replicated shared memory compared to shared virtual memory when the length of the network is large. While replicated shared memory using external memory is influenced by the ratio of local and global accesses, replicated shared memory using internal machine memory is suitable for a wide variety of cases. The replicated shared memory model is considered to be suitable particularly for applications which impose real time operation in a widely distributed environment, since some latency hiding techniques such as context switching or data prefetching are not effective for real time demands.

In PCM integrated communication systems in which PCM telephone signals are transmitted and switched in an integrated manner, the clock frequency of the PCM signals in the whole network must be synchronized. Mutual synchronization was proposed for this purpose. This is an important application of a phase-locked oscillator. By interconnecting two phase-locked oscillators to control each other, the frequency of the interconnected system will be the average of the free-running frequencies of the two oscillators. By interconnecting a number of multiple input phase-locked oscillators, all the oscinators can be synchronized. The synchronization system based on this principle is called mutual synchronization and various versions of mutually synchronized systems have been proposed. Since the interconnected system of phase-locked oscillators includes many positive and negative feedback loops, to design a system, the dynamic as well as the static behavior of the system should be carefully analyzed. This paper describes the principle of various versions of mutually synchronized systems and the results of analyses on the dynamic and static behavior of mutually synchronized systems.

A new channel assignment scheme called a frame addressing system is proposed in this paper to realize an efficient telephone subscriber carrier system by means of PCM loop having a simplified switching capability at each subscriber. In the frame addressing system, a speech signal time slot is assigned by sending a bit for each subscriber at the beginning of each transmission frame. This results in an improvement of efficiency by a TASI-like effect in addition to efficiency by switching. The principle and an example of a practical circuit are described. Characteristics of the system are analyzed and a design example is described.

Some means of time-slot interchanging is required in a pulse-code-modulation (PCM) transit switching system to satisfy the blocking requirements due to the fact that average trunk loading is high and that the time slots of incoming calls are preassigned at the remote office. This paper presents the use of serial-to-parallel conversion and parallel-to-serial conversion pulse shifters, both having limited time-slot interchange capability at the input and the output of the switching networks, respectively. The features of the system are that the required memory capacity is much smaller than the conventional systems and that serial transmission and parallel switching are possible. The results of optimization through blocking probability evaluation and network cost estimation are also described for networks with one, two, and three gate stages, and with an additional parallel pulse-shifter stage.