The paper proposes a novel practical replacement of conventional high-speed clock-gates for wide voltage scaling. The proposed clock-gate enhances the energy-delay-product by 43% and improves the low-voltage operation by 50 mV reducing the sampling window by 31% as compared with a conventional high-speed pulse-base clock-gate. The comparison also indicates 50% speed improvement resulting in up to 60% EDP reduction as compared with conventional low-power clock-gates. A test chip was fabricated using a 14 nm CMOS FinFET process with five representative process corners, SS, TT, FF, SF and FS, and measured under three temperature conditions, −25°C, 25°C and 100°C, for production-level silicon verification.

Novel high-speed low-power pulse-based flip-flops having a pulse generator controlled by scan input and scan enable signals are presented. The proposed scheme enables the reduction of data-to-output delay by elimination of the MUX-scan logic from the setup time path of flip-flop, at the cost of a small power overhead. The comparison results using the 45 nm CMOS process indicate that the worst-case DQ delay of the proposed flip-flop is reduced by up to 59% while the energy-delay product is improved by up to 80% compared to the conventional master-slave flip-flop. The silicon results show that the new flip-flops function properly down to 0.62 V.

Embedded systems make a heavy use of software to perform real-time embedded control tasks. Embedded software is characterized by a relatively long lifetime and by tight cost, performance and safety constraints. Several super-optimization techniques for embedded softwares based on multi-valued decision diagram (MDD) representations have been described in the literature, but they all share the same basic limitation. They are based on standard ordered MDD (OMDD) packages, and hence require a used order of evaluation for the MDD variables on every execution path. Free MDDs (FMDDs) lift this limitation, and hence open up more optimization opportunities. Finding the optimal variable ordering for FMDDs is a very difficult problem. Hence in this paper we describe a heuristic procedure that performs well in practice, and is based on FMDD cost estimation applied to recursive cofactoring. Experimental results show that our new variable ordering method obtains often. Smaller embedded software than previous (sifting-based) methods.

FPGAs are widely used for logic emulation, software acceleration, custom computing, and prototyping. The architecture (or the interconnect mechanism of a FPGA network) of an emulator has profound effect on the performance (speed) and efficiency (chip utilization) of the emulator. In this paper, several architectures of FPGA networks are suggested, and they are compared with other typical existing architectures by using the MCNC partition benchmark circuits. Experimental results show that tripartite network outperforms six other typical architectures both in performance and in efficiency. For this study, the propagation delay of a path is estimated by the number of hops (interchip connections) and the number of intrachip connections on the path, and thus it is independent of a specific FPGA type. To partition a given circuit into the given prerouted network of FPGAs, a new routability-driven partitioning algorithm is developed. Experimental results using the MCNC benchmark examples show that our partition method produces better results than those of other recent approaches on the average, and that performance-driven partitioning is effective in reducing critical time delays.

No abstract available.

An efficient and effective optimization technique is developed for technology mapping of lookup table (LUT) based field programmable gate arrays. In our algorithm, minimal depth of a Boolean network is found and then the given cost function is minimized by "sweeping" nodes of the given Boolean network without increasing the depth. The sweeping allows an efficient search over a huge solution space since it utilizes the topological structure of the network. Optimization for reconvergent paths and duplication of logic can be automatically considered during the sweeping procedure. Experimental results show that our approach is very promising. Typically our method, called SWEEP, produced the same depth for the 17 benchmark circuits tried as those of FlowMap which guarantees the optimum depth. Furthermore, SWEEP outperforms FlowMap by 17% in the total number of LUT's required to implement the benchmark circuits.>

A hierarchical placement algorithm which combines mincut partitioning and simulated annealing has been developed. The objective of mincut partitioning is to minimize the number of crossing nets while the objective of placement by simulated annealing is usually to minimize the total estimated wire-length. The combined placement algorithm can optimize both the routing density and the estimated wire-length. For efficiency, the placement is performed using multiple levels of hierarchy in the top-down direction, i.e., big groups of cells are placed at the beginning and leafcells are placed at the final level. Several standard-cell and sea-of-gates circuits are placed using the combined placement techniques and promising results are obtained when compared with those of several other placement methods.

Partitioning is an important step in the top-down design of large complicated integrated circuits. In this paper, a simple yet effective partitioning technique is described. It is based on the clustering of "closely" connected cells and the gradual enforcement of size-constraints. At the beginning, clusters are formed in the bottom-up fashion to reduce the problem size. Then the clusters are partitioned using several different parameters to find a good starting point. The best result achieved during the cluster partitioning is used as the initial solution for the lower level partitioning. The gradual constraint enforcement technique is used to cope with the local minimum problems. It allows cells or clusters to move with more freedom among the subsets during earlier iterations and thus may effectively find a near optimum solution. Several experimental results show that the new partitioning technique produces favorable results. In particular, the method outperforms the F&M method by more than 60% in the number of crossing nets on average.>