Demo Data from EDBT 2026 / reviewers in the wild / expert
Chun Liu 0001
dblp:67/1749-1
· DBLP profile ↗
4ranked-venue papers
3as first author
0since 2021 · last 2006
—ORCID · conflict
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Memory systems · 70% Processor architecture and microarchitecture · 23% Performance modeling and evaluation · 7% |
Topics — the 5 heaviest of 5, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Memory systems › memory hierarchy
cache hierarchy |
0.0 | 1 | 2004 | Organizing the Last Line of Defense before Hitting the Memory Wall for CMP · HPCA 2004 |
Memory systems › cache
cache organization |
0.0 | 1 | 2004 | Organizing the Last Line of Defense before Hitting the Memory Wall for CMP · HPCA 2004 |
Processor architecture and microarchitecture
chip multiprocessor |
0.0 | 1 | 2004 | Organizing the Last Line of Defense before Hitting the Memory Wall for CMP · HPCA 2004 |
Memory systems › cache design
last-level cache organization |
0.0 | 1 | 2004 | Organizing the Last Line of Defense before Hitting the Memory Wall for CMP · HPCA 2004 |
Performance modeling and evaluation
simulation |
0.0 | 1 | 2004 | Organizing the Last Line of Defense before Hitting the Memory Wall for CMP · HPCA 2004 |
Methods — techniques the papers use, named apart from their topics
shared processor-based split l2 · 0.0address-interleaved shared l2 · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2006 | Enhancing L2 organization for CMPs with a center cellabstractChip multiprocessors (CMPs) are becoming a popular way of exploiting ever-increasing number of on-chip transistors. At the same time, the location of data on the chip can play a critical role in the performance of these CMPs because of the growing on-chip storage capacities and the relative cost of wire delays. It is important to locate the data at the right place at the right time in the on-chip cache hierarchy. This paper presents a novel L2 cache organization for CMPs with these goals in mind. We first study the data sharing characteristics of a wide spectrum of multi-threaded applications and show that, while there are a considerable number of L2 accesses to shared data, the volume of this data is relatively low. Consequently, it is important to keep this shared data fairly close to all processor cores for both performance and power reasons. Motivated by this observation, we propose a small center cell cache residing in the middle of the processor cores which provides fast access to its contents. We demonstrate that this cache organization can considerably lower the number of block migrations between the L2 portions that are closer to each core, thus providing better performance and power. Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir, Mary Jane Irwin |
IPDPS | 1 |
| 2006 | Optimizing bus energy consumption of on-chip multiprocessors using frequent values
Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir |
J. Syst. Archit. | 1 |
| 2004 | Organizing the Last Line of Defense before Hitting the Memory Wall for CMPabstractThe last line of defense in the cache hierarchy before going to off-chip memory is very critical in chip multiprocessors (CMPs) from both the performance and power perspectives. We investigate different organizations for this last line of defense (assumed to be L2 in this article) towards reducing off-chip memory accesses. We evaluate the trade-offs between private L2 and address-interleaved shared L2 designs, noting their individual benefits and drawbacks. The possible imbalance between the L2 demands across the CPUs favors a shared L2 organization, while the interference between these demands can favor a private L2 organization. We propose a new architecture, called Shared Processor-Based Split L2, that captures the benefits of these two organizations, while avoiding many of their drawbacks. Using several applications from the SPEC OMP suite and a commercial benchmark, Specjbb, on a complete system simulator, we demonstrate the benefits of this shared processor-based L2 organization. Our results show as much as 42.50% improvement in IPC over the private organization (with 11.52% on the average), and as much as 42.22% improvement over the shared interleaved organization (with 9.76% on the average). Chun Liu 0001, Anand Sivasubramaniam, Mahmut T. Kandemir |
HPCA | 1 |
| 2003 | Decision-Support Workload Characteristics on a Clustered Database Server from the OS PerspectiveabstractA range of database services are being offered on clusters of workstations today to meet the demanding needs of applications with voluminous datasets, high computational and I/O requirements and a large number of users. The underlying database engine runs on cost-effective off-the-shelf hardware and software components that may not really be tailored/tuned for these applications. At the same time, many of these databases have legacy codes that may not be easy to modulate based on the evolving capabilities and limitations of clusters. An indepth understanding of the interaction between these database engines and the underlying operating system (OS) can identify a set of characteristics that would be extremely valuable for future research on systems support for these environments. To our knowledge, there is no prior work that has embarked on such a characterization for a clustered database server. Using IBM DB2 Universal Database (UDB) Extended Enterprise Edition (EEE) V7.2 Trial version and TPC-H like/sup 1/ decision support queries, this paper studies numerous issues by evaluating performance on an off-the-shelf Pentium/Linux cluster connected by Myrinet. These include detailed performance profiles of all kernel activities, as well as qualitative and quantitative insights on the interaction between the database engine and the operating system. Yanyong Zhang, Jianyong Zhang, Anand Sivasubramaniam, Chun Liu 0001, Hubertus Franke |
ICDCS | 4 |