Since the IC technology scales down the effect of voltage drop/ground bounce becomes increasingly significant. Voltage drop and ground bounce can compromise the gate driving capability and degrade the IC performance, and even can cause IC functional failures. Hence, it is crucial to capture this effect efficiently and accurately in order to improve circuit reliability. in this paper, we propose efficient modeling techniques for analyzing power distribution in deep sub micron (DSM) ASIC designs. Current Source-based Model (CSM) and Voltage Controlled Resistor (VCR) are the key concepts in our approach. A basic prerequisite for the new approach are CMOS standard libraries that are pre-characterized with respect to the corresponding modeling requirements. This paper also presents an approach for this characterization step. The proposed techniques can efficiently handle multiple-input-switching (MIS), including single-input-switching events (SIS) and provide good analysis results compared to the reference with two orders of magnitude speedup, although the cell library pre-characterization is based on SPICE simulations. Our model is independent of the power network context, which implies that different power distribution networks may be analyzed based on the same model and the same cell characterizations. The run-time, memory and accuracy efficiency of the proposed method are demonstrated on an industrial design.