Demo Data from EDBT 2026 / reviewers in the wild / expert
Harold W. Carter
dblp:67/2318
· DBLP profile ↗
8ranked-venue papers
2as first author
0since 2021 · last 2009
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 7 · 2 first-authorSoftware engineering, systems software and programming languages · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Performance modeling and evaluation · 72% Electronic design automation · 17% Parallel and multicore computing · 11% | |
| Software engineering, system software, and programming languages
1 paper |
Program verification · 100% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Program verification
theorem proving |
0.0 | 1 | 2002 | A Formal Specification and Verification Framework for Time Warp-Based Parallel Simulation · IEEE Trans. Software Eng. 2002 |
Performance modeling and evaluation › simulation › discrete-event simulation
parallel discrete event simulation |
0.0 | 1 | 2002 | A Formal Specification and Verification Framework for Time Warp-Based Parallel Simulation · IEEE Trans. Software Eng. 2002 |
Performance modeling and evaluation › simulation › discrete-event simulation › parallel discrete event simulation › optimistic simulation
time warp |
0.0 | 1 | 2002 | A Formal Specification and Verification Framework for Time Warp-Based Parallel Simulation · IEEE Trans. Software Eng. 2002 |
Parallel and multicore computing › synchronization
optimistic synchronization |
0.0 | 1 | 2002 | A Formal Specification and Verification Framework for Time Warp-Based Parallel Simulation · IEEE Trans. Software Eng. 2002 |
Electronic design automation
physical design |
0.0 | 2 | 1983 | Efficient Single-Layer Routing Along a Line of Points · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 Incremental processing applied to Steinberg's placement procedure · DAC 1979 |
Electronic design automation › physical design › routing
channel routing |
0.0 | 1 | 1983 | Efficient Single-Layer Routing Along a Line of Points · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design › routing › multilayer routing
layer assignment |
0.0 | 1 | 1983 | Efficient Single-Layer Routing Along a Line of Points · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design
routing |
0.0 | 1 | 1983 | Efficient Single-Layer Routing Along a Line of Points · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design › routing › VLSI routing
single-layer routing |
0.0 | 1 | 1983 | Efficient Single-Layer Routing Along a Line of Points · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1983 |
Electronic design automation › physical design › placement
detailed placement |
0.0 | 1 | 1979 | Incremental processing applied to Steinberg's placement procedure · DAC 1979 |
Electronic design automation › physical design
placement |
0.0 | 1 | 1979 | Incremental processing applied to Steinberg's placement procedure · DAC 1979 |
Methods — techniques the papers use, named apart from their topics
model checking · 0.1PVS · 0.1LTL · 0.1optimal path search · 0.0floating-track assignment · 0.0access graph · 0.0steinberg's placement procedure · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2009 | A taylor series methodology for analyzing the effects of process variation on circuit operationabstractWe present a methodology that can analyze the effect of process variations without requiring the repeated simulations of a Monte Carlo type method. A graph theoretic procedure is described to obtain an explicit differential equation from the differential algebraic equations modeling a circuit netlist. With this explicit form, Taylor series polynomials are used to represent the system variables. The non-constant process parameters are represented as intervals, the Taylor series expansion is used to perform interval computations to generate bounds for the system variables. Methods are discussed to prevent blow-up of intervals during the time marching method. Raghuram Srinivasan, Harold W. Carter |
ACM Great Lakes Symposium on VLSI | 2 |
| 2008 | Fast multivariate signature generation in hardware: The case of rainbowabstractThis paper presents a time-area efficient hardware architecture for the multivariate signature scheme Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation are presented. The resulting signature generation core of Rainbow requires 63,593 gate equivalents and signs a message in just 804 clock cycles at 67 MHz using AMI 0.35μm CMOS technology. Thus, Rainbow provides significant performance improvements compared to RSA and ECDSA. Sundar Balasubramanian, Harold W. Carter, Andrey Bogdanov, Andy Rupp, Jintai Ding |
ASAP | 2 |
| 2008 | Fast Multivariate Signature Generation in Hardware: The Case of RainbowabstractThis paper deals with the design of an area-time efficient hardware architecture for the multivariate signature scheme, Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation is presented. Besides solving LSEs, the architecture is also re-used for the linear transformation operations of the scheme, thereby saving on area. The resulting signature generation core of Rainbow requires 63,593 gate equivalents and signs a message in just 804 clock cycles. A comparison of our architecture with implementations of the RSA, the ECDSA and the en-TTS scheme shows that Rainbow in hardware provides significant performance improvements. Sundar Balasubramanian, Andrey Bogdanov, Andy Rupp, Jintai Ding, Harold W. Carter |
FCCM | 5 |
| 2002 | A Formal Specification and Verification Framework for Time Warp-Based Parallel SimulationabstractThe paper describes a formal framework developed using the Prototype Verification System (PVS) to model and verify distributed simulation kernels based on the Time Warp paradigm. The intent is to provide a common formal base from which domain specific simulators can be modeled, verified, and developed. PVS constructs are developed to represent basic Time Warp constructs. Correctness conditions for Time Warp simulation are identified, describing causal ordering of event processing and correct rollback processing. The PVS theorem prover and type-check condition system are then used to verify all correctness conditions. In addition, the paper discusses the framework's reusability and extensibility properties in support of specification and verification of Time Warp extensions and optimizations. Peter Frey, Radharamanan Radhakrishnan, Harold W. Carter, Philip A. Wilsey, Perry Alexander |
IEEE Trans. Software Eng. | 3 |
| 2001 | Optimizing Costs of Web-based Modeling and SimulationabstractWeb-based simulations are performed by utilizing the resources of the Word Wide Web (WWW) such as proprietary components/models developed by third party modelers /manufacturers and web-based computational infrastructures (or compute servers). Access to such web-based resources, third party resources in particular, is usually circumscribed by a variety of pricing schemes. Therefore, optimal use of resources plays a critical role in minimizing the overall costs of web-based modeling and simulation which is directly dependent on the size of the model i.e., the total number of components constituting the model. Consequently, component aggregation and de-aggregation techniques that can be used to statically (before simulation) as well as dynamically (during simulation) vary the number of components constituting a model, have been developed. The techniques enable a range of tradeoffs between several modeling and simulation related parameters -- thereby optimizing the resource consumption and overall costs. This paper presents a detailed discussion of the component aggregation and de-aggregation techniques along with the issues involved in implementing them in a Web-based Environment for Systems Engineering (WESE). Our studies indicate that these techniques provide an effective means to optimize the overall costs of web-based modeling and simulation. Dhananjai Madhava Rao, Harold W. Carter, Philip A. Wilsey |
IPDPS | 2 |
| 1997 | Parallel Synchronization of Continuous Time Discrete Event SimulatorsabstractMixed-Mode simulation has been generating considerable interest in the simulation community and has continued to grow as an active research area. Traditional mixed-mode simulation involves the merging of digital and analog simulators in various ways. However, efficient methods for the synchronization between the two time domains remains elusive. This is due to the fact that the analog simulator uses dynamic time step control whereas the digital simulator uses the event driven paradigm. This paper proposes two new synchronization methods and presents their capabilities using a component-based continuous time simulator integrated with an optimistic parallel discrete event simulator. The results of the performance evaluation leads us to believe that while both synchronization methods are functionally viable, one has superior performance. Peter Frey, Harold W. Carter, Philip A. Wilsey |
ICPP | 2 |
| 1983 | Efficient Single-Layer Routing Along a Line of PointsabstractIn this paper we present several new procedures for carrying out the track assignment phase involved in channel routing. Our procedures are based upon the concept of an access graph which provides information dealing with the availability of routing space between pins in a layout. Paths for signal nets are then found by searching for optimal paths in the access graph. These paths can then be easily mapped back into routed wire segments on a VLSI chip. We consider only the case of single-layer routing within a single channel. We allow for wires to be on both sides of the line of pins to be processed, as well as between the pins. We consider two models, the first where the track availability is infinite, or equivalently, where wires are infinitely thin. We then consider the more realistic case where the track density in the channel is fixed. Our procedure for this case, called floating-track assignment, allows a wire, once assigned to a track, to be reassigned to a different track in order to enhance routability. For this case, we consider three objective functions, namely, minimal wire length, minimal congestion, and minimal perturbation. Both theoretical and experimental results are presented. Harold W. Carter, Melvin A. Breuer |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1979 | Incremental processing applied to Steinberg's placement procedure
Harold W. Carter, Melvin A. Breuer, Zahir A. Syed |
DAC | 1 |