Predicting the Single-Event Effects in integrated circuits before their fabrication and ultimately estimating their cross-section would be of much interest to the space industry. For high-performance analog and mixed-signal circuits, radiation-hardening design flows routinely include Single-Event electrical simulation to identify the most sensitive nodes. If we can identify the sensitive area of the circuit to the PN-diodes connected to the sensitive nodes, we should thus be able to get an estimate of the cross-section. In this work, we show that this is far from being reality by comparing the results of electrical simulations to the cross-sections obtained by radiating a rad-hard reference generator for a high-performance ADC with Heavy Ions. A deep analysis of the results suggests that there are unmodelled effects at stake that dominate the experimental cross-section.

One of the most critical radiation effects, because it is potentially destructive, is the Single-Event Latchup (SEL). Positive feedback in parasitic bipolar structures, triggered by a current pulse induced by an ionizing particle, creates a low impedance path between supply and ground. If the supply is not rapidly shut down, high currents can cause burnout or metal opens. Any radiation campaign must thus implement some protection at the board level to properly detect the onset of a latchup and shut the circuit power down. This paper describes an SEL detection platform, designed for a 13b 40Msps ADC prototype, that takes into account the specific requirements of high-precision Analog and Mixed-Signal circuits.

This article proposes a behavioral model, based on closed-form equations, of the dynamic errors in high-speed high-accuracy successive approximation register (SAR) analog-to-digital converters (ADCs) with charge-redistribution capacitor-based digital-to-analog converters (CDACs). To deal with incomplete settling of references and overcoming$LC$package parasitics, on-chip generation of the references must be considered in high-performance applications. This architecture, in combination with a bit-redundant conversion scheme, improves conversion speed while relaxing power consumption. The main challenge in this approach is that the reference settling and the resulting redundancy tolerance are signal-dependent, not only on the current error magnitude but also on the previous conversion cycle history and parasitics. This requires costly postlayout transistor-level simulations for performance evaluation (in the order of days), making not always feasible a systematic exploration of design space before integration due to computation time. To overcome this bottleneck, this work will show that the dynamic behavior can be theoretically predicted using a time-varying effective reference, the behavior of which is analytically described compactly. The accuracy of the proposed dynamic model is verified with a comparison with a 1.2-V 13-bit 65-nm SAR ADC characterized between 10 and 60 Msps at the postlayout level.

This paper presents a novel Look-up Table (LUT) calibration technique for static non-linearity compensation in analog-to-digital converters (ADCs) with digital redundancy, such as Successive Approximation Register (SAR), Algorithmic, Sub-ranging or Pipeline ADCs. The method compensates the performance limitations of the conventional LUT approach in presence of comparison noise and/or non-monotonicity. In these circumstances, the input-output transfer function of a redundant ADC becomes significantly multivalued - that is, different output codes can be achieved for the same input level at different time instants. This behavior is motivated because from sample to sample, in a design with redundancy, the processing signal path is not unique, causing that the error under calibration becomes time-dependent, something which is not contemplated in the conventional calibration model. To deal with this effect, this work proposes a digital low-cost post-processing of the standardized Integral-Non-linearity (INL), which resolves multivalued situations using a direct access to the internal redundant codes. The method improvements are validated by realistic SAR and Pipeline ADC case studies at behavioral level, and by experimental data from an 11-bit 60Msps Pipeline ADC implemented in a 130nm CMOS process. These experimental results show that the proposed calibration achieves an improvement of approximately 1.6 effective bits at full-scale input amplitude.

This paper presents a robust method to perform capacitor mismatch calibration in a redundant SAR ADCs correcting the effect of comparator static offset in the calibration process. Without proper handling of this effect, capacitor miscalibration can occur due to saturation of the redundancy intervals associated with implemented weights, eventually leading to a faulty behavior even with lower effective resolution than the case without calibration. To overcome this limitation, this work proposes a foreground technique which reuses the least-significant bit (LSB) capacitors in the array in a design with redundancy for offset compensation. The effectiveness of the method is demonstrated by realistic behavioral simulations in a 12-bit SAR ADC case study with 3 redundant bits.

This paper presents a new simulation method for fast evaluation of non-linear circuits. The proposed approach solves the non-linear ordinary differential equation (ODE) set of the system using a semi-analytical solution based on the matrix exponential. The method is fully general and suitable for different circuits, including switched-capacitor (SC) architectures, analog to digital converters (Pipeline, SAR, Sigma-Delta ADCs) or digital to analog converters. For illustration purpose in this paper, an analog signal processing front-end for discrete-time data acquisition system is considered as case study. The circuit comprises a Flip-Around Sample&Hold followed by a Programmable Gain Amplifier (PGA), based on a Correlated Double-Sampling amplifier, and a back-end ADC. The model includes non-linearity associated to switches, capacitive parasitics, finite nonlinear DC-gain and non-linear settling behavior including slew-rate. Comparison with traditional ODE numerical solvers shows a reduction of the computation time in almost two orders of magnitude with negligible difference in terms of accuracy.

This paper analyzes the state-of-the-art in Successive-Approximation-Register (SAR) ADCs with digital redundancy using a unified nomenclature and modeling. Redundancy provides tolerance intervals for dealing with comparison errors during the SAR search algorithm due to incomplete settling in the DAC. Employing redundancy improves conversion speed/power trade-off as well as relaxes switch sizes and comparator design. The proposed description presents a common theoretical and physical framework for analyzing existing (apparently different) techniques in the bibliography, independently of the practical realization (binary or arbitrary scaled capacitors with redundant bits) and switching schemes. Several examples are modeled and simulated using the proposed approach.

Testing analog, mixed-signal and RF circuits represents the main cost component for testing complex SoCs. A promising solution to alleviate this cost is the machine learning-based test strategy. These test techniques are an indirect test approach that replaces costly specification measurements by simpler signatures. Machine learning algorithms are used to map these signatures to the performance parameters. Although this approach has a number of undoubtable advantages, it also opens new issues that have to be addressed before it can be widely adopted by the industry. In this paper we present a machine learning-based test for a complex mixed-signal system - i.e. a state-of-the-art pipeline ADC-that includes digital calibration. This paper shows how the introduction of digital calibration for the ADC has a serious impact in the proposed test as calibration completely decorrelates signatures from the target specification in the presence of local mismatch.

This brief presents a digital calibration technique for compensating timing-skew errors between the sub-ADC and the MDAC in the first stage of sample-and-hold amplifier (SHA)-less pipeline ADCs. In the presence of clock-skew errors, sub-ADC comparators produce time-variant offsets depending on the input-signal slope at the sampling instants. These increase residue excursions at the MDAC output, potentially causing overranging and an increment in nonlinear errors. This paper derives close analytical expressions for these effects. The proposed method uses the overranging information to perform a low-cost estimation and correction of the skew error with the following features: 1) very fast convergence (in the order of 1-k input samples); 2) indirect evaluation of the skew error signal, without any previous knowledge of the input signal's frequency distribution; and 3) relatively simple digital logic-basically, two digital comparators and one small accumulator. The method was verified in behavioral and transistor-level simulations. As a demonstrator, its implementation in a 1.8-V 80-dB SNDR 100-Msps SHA-less pipeline ADC in a 0.18-μm CMOS process is shown.

This paper presents a self-testable BIST application for non-linearity test in high-speed high-performance ADCs in nanometric CMOS technologies. The technique makes use of an on-chip low-frequency signal generator optimized toward high accuracy, followed by a dedicated buffer based on a resistive feedback amplifier. This buffer has two main features: it isolates the on-chip generator output from the high-frequency switching noise at the input sampling of the ADC under test, and it allows a robust injection of a controlled offset to apply double-histogram techniques for linearity evaluation. This approach results in a true self-testable BIST strategy making feasible the simultaneous estimation of the non-linearity for both the generator and the ADCUT. In order to verify the feasibility and performance of the proposed circuitry, a practical design in a 1.8V 0.18μm CMOS process is presented here as demonstrator. Transistor-level simulation results with a 2Vpp sinusoidal test-stimulus show an effective resolution in static conditions greater than 15 bits, being a suitable solution for the ADC static test with effective resolutions in the order of 13 bits and 100Msps of sampling frequency.

This brief presents a low-cost digital technique for background calibration of comparator offsets in pipeline analog-to-digital converters (ADCs). Thanks to calibration, comparator offset errors above half the stage least-significant bit margin in a unitary redundancy scheme are admissible, thus relaxing comparator design requirements and allowing their optimization for low-power high-speed applications and low input capacitance. The technique also makes it possible to relax design requirements of stage amplifiers within the pipeline queue, since output swing and driving capability are significantly lower. In this brief, the proposal is validated using realistic hardware-behavioral models.

This paper presents a procedure to implement a high efficient test of the Integral Non-linearity (INL) of Pipeline ADCs using an extremely reduced set of test input amplitude levels (one order of magnitude lower than the total number of codes in the ADC). For a given architecture, the method provides the way to determine these levels to robustly capture the nonlinearity information. The location of each test level within the input range has low sensitivity to the internal ADC noise, and therefore, they are a good basis to continuously monitor the impact of process, aging and environment conditions variations (PVT) on the non-linearity, as well as miscalibration and possible failures in both foreground and background applications. The proposed method has been validated by realistic behavioral models in several examples.

This paper analyzes the common-mode response of LC voltage-controlled oscillators (VCOs) in DC and periodic steady state regimes. The dependence of the common-mode voltage (vcm) on the oscillation amplitude is theoretically studied. Closed and simple expressions for vcmsuitable for the VCO design and optimization are derived. The agreement with transistor level simulations has been verified in a 1.2V low-power 90nm CMOS case of study.

In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude between 0°C and 100°C with negligible impact on the phase noise. Worst case estimations of the VCO phase noise after layout parasitic extraction are -110.1dBc/Hz and -126.6dBc/Hz at 1MHz and 5MHz offsets from the carrier, respectively. Its nominal current consumption is 198μA (plus 22.5μA for biasing) and it occupies 370×530μm2.

A unified description of the correlation-based techniques for background calibration of pipeline ADCs using additive modulation at the MDAC output is presented in this paper. Two different algorithms for full calibration of this kind of converter which at least a factor 2 improvement in convergence speed, memory resources and stage output swing requirements over previous MDAC modulation approaches are also proposed.

This paper presents a theoretical analysis of the statistical requirements of a background correlation-based technique for calibration of pipeline ADCs. The calibration algorithm estimates adaptively the appropriate additive error codes which compensate both the gain and non-linear errors in the stage under calibration (SUC). Close equations for the transient evolution towards the stationary situation are obtained. Expressions for the effective number of bits (ENOB) and signal-to-noise ratio (SNR) at any updating step are also derived

This paper presents a new digital technique for background calibration of gain errors in pipeline ADCs. The proposed algorithm estimates and corrects both the MDAC gain error of the stage under calibration and the global gain error associated to the uncalibrated stages without interruption of the conversion and without reduction of the dynamic rate. It is based on the use of a stage with two input-output characteristics, depending on the value of a digital noise signal.

Current system-on-chip (SoC) designs incorporate an increasing number of mixed-signal components. Design reuse techniques have proved successful for digital design but these rules are difficult to transfer to mixed-signal design. A top-down methodology is missing but the low level of abstraction in designs makes system integration and verification a very difficult, tedious and complex task. This paper presents a contribution to mixed-signal design reuse where a design methodology is proposed based on modular and parametric behavioural components. They support a design process where non-ideal effects can be incorporated in an incremental way, allowing easy architectural selection and accurate simulations. A working example is used through the paper to highlight and validate the applicability of the methodology.

The application of design reuse to analog and mixed-signal components for System-on-Chip (SoC) is an emerging and revolutionary field. This paper presents a methodological approach to this area illustrated with a mixed-signal case study.

This paper presents a BIST scheme for the structural testing of pipelined ADCs. The operational principle relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a set of analog DC values. These values have been determined as the appropriate and simple stimuli giving a single output signature. A new output signature is proposed allowing a low-cost digital domain test evaluation. The new technique is intended to be used in pipelined converters of an arbitrary number of conversion stages and provided with a digital correction mechanism.

This paper presents an operational method for converting into digital the analog waveforms resulting when oscillation-based test (OBT) is applied to a mixed signal integrated circuit. Although our aim is OBT this technique can be used in structural testing in general. A complex mixed-signal macrocell is used as an example to demonstrate the pros and cons of the technique.

This paper proposes a methodology for designing sampled-data mixed-signal circuits by using VHDL-based behavioural descriptions. The goal is using a VHDL description of both the analog and the digital part, to simulate and verify the entire mixed-signal system, as well as to facilitate the synthesis and fault simulation of the digital part. As an example of the proposed methodology, a digitally corrected/calibrated pipeline A/D converter (ADC) has been designed. Among other aspects of general interest, we show how analog dynamic effects are incorporated in order to obtain accurate high level simulations. Results from simulations carried out using QuickHDL in MentorGraphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a silicon prototype.

This paper proposes a behavioural model for digitally corrected/calibrated pipeline A/D converters (ADCs) based on standard VHDL. We will show how VHDL-based analog modelling can be efficiently used to simulate and verify the functionality of these mixed-signal systems where significant interaction exists between analog and digital parts. The main motivation for describing the behavioural model (analog and digital) directly in standard VHDL is to make possible the synthesis and fault simulation of the digital part using standard digital tools. Results from simulations carried out using QuickHDL in Mentor-Graphics prove the feasibility of the approach and are in agreement with those obtained experimentally from a Silicon prototype.

This paper presents an approach towards realistic fault prediction in analog circuits. It exploits the Inductive Fault Analysis (IFA) methodology to generate explicit models able to give the probability of occurrence of faults associated with devices in an analog cell. This information intends to facilitate the integration of design and test phases in the development of an IC since it provides a realistic fault list for simulation before going to the final layout, and also makes possible layout optimization towards what we can call layout level design for testability.

This paper addresses the practical implementation of a Design-for-Testability (DfT) technique applicable to digitally-corrected pipelined Analog-to-Digital Converters (ADC). The objective of this Dft is to improve both the on-and off-line testability of these important mixed-signal ICs. Because of the self-correction capability, such a kind of converters has some inherent insensitivity to the effect of faults which represents a disadvantage for testing and diagnosis. We will show that potentially malfunctioning units can be concurrently identified with low extra circuitry. In addition, this structure-based DfT scheme can also be useful to reduce the time in production-level testing. A CMOS switched-capacitor 10-b ADC is used as demonstrator of the proposed technique.

A tool for the switch-level fault simulation and test evaluationof switched-capacitor systems is presented. Time or frequency-domainfault simulations with SWITCAP and time-domain faultsimulations with HSPICE can be performed. Adequate fault modelsare presented for both simulators. The tool has proven to bevery useful in the early evaluation of test strategies, providing similarresults to those obtained at the transistor-level.

Pipeline or sub-ranging architectures enable the implementation of high-speed, low-power and high-resolution Analog-to-Digital Converters (ADCs). It is usual in these architectures to include digital correction to reduce the sensitivity to certain component nonlinearities, such as comparator offsets and settling errors. However, digital correction makes difficult the detection of defective operation because some errors could not be revealed in the output code under nominal test conditions but could appear when operation conditions change. This paper presents a Design-for-Testability (DFT) technique for concurrent error detection in digitally-corrected pipelined ADCs. The approach is based on hardware redundancy, requiring an additional sub-DAC, a window comparator and some control logic. The effectiveness of the technique has been evaluated by means of fault simulations in a switched-capacitor 10-bit ADC application example.

This paper presents a method to characterize Nyquist rate A/D converters based on the use of a first order statistical behavioral model. The proposed model is derived from a very basic statistical interpretation of the conversion operation which contemplates noise and statistical process variations effects on traditional converter parameters. Both DC and dynamic converter parameters can be easily measured. The applicability of the proposed method is illustrated with two different examples. The first serves to show the possibility of deriving the statistical behavioral model from real measured data, and to prove the correctness of the model by comparing results to those obtained with traditional deterministic models. The second example illustrates the incorporation of the model in the mixed-signal simulator ELDO. The obtained results show that despite the model's simplicity, it is very efficient for quick and complete simulation of data converters.