Power has become a critical concern for battery-driven computing systems, on which many applications that are run are interactive. System-level voltage scaling techniques, such as dynamic voltage scaling (DVS) and adaptive body biasing (ABB), have been shown to reduce energy consumption effectively. Previous works on DVS and ABB exploit low CPU utilization of the processor to drive voltage scaling. This has become inadequate for modern interactive applications involving high CPU usage. In this work, we target computer responsiveness during voltage scaling to exploit more opportunities for energy reduction. Instead of CPU utilization, we use the user-perceived latency, the delay between user input and computer response, to drive voltage scaling. Considering the tradeoff between energy consumption and computer responsiveness during voltage scaling not only reduces energy consumption effectively, but also ensures good computer responsiveness for interactive applications. Experimental results show that for the 70nm technology, during the execution of seven commonly-used interactive applications, the energy consumption of the processor using user-perceived latency driven DVS is reduced by an average of 37.3%, and the user-perceived latency by an average of 18.3%, compared to CPU utilization driven DVS. If both DVS and ABB are performed simultaneously based on the user-perceived latency, then the energy consumption is reduced by another 38.9% compared to when DVS is performed alone, while maintaining a similar computer responsiveness level. We have implemented user-perceived latency driven voltage scaling under Linux with X Window system. However, the methodology is extensible to other operating systems as well.

Although computing hardware has become increasingly more powerful, computer responsiveness is still an important issue due to multi-tasking and software bloat. We propose a holistic approach for improving computer responsiveness through user focus-aware resource management for CPU, memory, disk I/O, and graphics processing. Previous approaches only address one or two of these problems simultaneously. To the best of our knowledge, our work is the first to address disk I/O scheduling for better responsiveness. It also offers better solutions for the other problems. We also exploit the user-perceived latency to perform dynamic voltage scaling of the CPU to reduce power consumption at run-time without sacrificing responsiveness. We implemented our approach in the Linux/X Window system (henceforth referred to as Linux/X) on an IBM Thinkpad R32 laptop with mobile Pentium 4-M processor, which has two performance levels with different frequency/supply voltage settings: high (30.0W at 1.8GHz/1.3V) and low (20.8W at 1.2GHz/1.2V). Experimental results show that user focus-aware resource management achieves a significant improvement in computer responsiveness and some in energy efficiency. For example, for TuxRacer, a video racing game, with GpsDrive, a navigation system, running in the background, it provides a reduction of 42.0% in user-perceived latency and 7.5% in energy consumption with respect to the Linux/X system.

While dynamic power consumption has traditionally been the primary source of power consumption, leakage power is becoming an increasingly important concern as technology feature size continues to shrink. Previous system-level approaches focus on reducing power consumption without considering leakage power consumption. To overcome this limitation, we propose a two-phase approach to combine dynamic voltage scaling (DVS) and adaptive body biasing (ABB) for distributed real-time embedded systems. DVS is a powerful technique for reducing dynamic power consumption quadratically. However, DVS often requires a reduction in the threshold voltage that increases subthreshold leakage current exponentially and, hence, subthreshold leakage power consumption. ABB, which exploits the exponential dependence of subthreshold leakage power on the threshold voltage, is effective in managing leakage power consumption. We first derive an energy consumption model to determine the optimal supply voltage and body bias voltage under a given clock frequency. Then, we analyze the tradeoff between energy consumption and clock period to allocate slack to a set of tasks with precedence relationships and real-time constraints. Based on this two-phase approach, we propose a new system-level scheduling algorithm that can optimize both dynamic power and leakage power consumption by performing DVS and ABB simultaneously for distributed real-time embedded systems. Experimental results show that the average power reduction of our technique with respect to DVS alone is 37.4% for the 70-nm technology.