EDBT 2026 Demo / reviewers in the wild / expert
Kevin G. McCarthy
dblp:67/2648
· DBLP profile ↗
5ranked-venue papers
0as first author
4since 2021 · last 2026
0000-0003-0624-4754ORCID · reported
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 4 · 3 since 2021Computer networks · 1 · 1 since 2021
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2026 | Cryogenic Influences on Frequency Dividers and Output Buffers in Ring-Oscillator Design and Characterization
Minda Wen, V. H. Arzate Palma, Ivan John O'Connell, Kevin G. McCarthy, Gerardo Molina Salgado |
ISCAS | 4 |
| 2025 | Open-Source 4 K CMOS Calibration: Integrating IceMOS and Sky130 PDKabstractWe present an open-source calibration methodology for Sky130 CMOS at $\mathbf{4 ~ K}$, focusing on robust initial extraction of threshold voltage (VTH0) and slope factor (n) via the SEKVE parameter-extraction tool. To address measurement noise, a partial Z-score filter is applied to the raw data, reducing extraction errors from above 10% to under 2%. These refined parameters then feed into an iterative BSIM4 calibration using IceMOS. As a result, the final calibrated Sky130 models achieve an accuracy in the strong inversion region with median error percentages of 9.49% for PMOS and just 1.11% for NMOS. Transconductance $g_{m}$ calibration is similarly precise with median errors of 5.95% and 2.46% for PMOS and NMOS, respectively, in the strong inversion region. By separating the SEKV-E and IceMOS steps yet integrating them into a fully open-source flow (including Docker-based ngspice simulations), our approach significantly minimizes manual intervention. The Sky130-compatible IceMOS scripts, Z-score routines, and calibrated device models are publicly available, reinforcing the open-source ecosystem for Cryo-CMOS research. Mauricio Montanares, V. H. Arzate Palma, Kevin G. McCarthy, Gerardo Molina Salgado |
VLSI-SoC | 3 |
| 2024 | A Low Power Programmable Switch Supply Dynamic ComparatorabstractThis paper introduces a programmable switch supply comparator that uses a programmable reservoir capacitor to achieve a reduced effective supply voltage during the decision phase. This comparator achieves up to 50% power consumption reduction against the conventional dynamic comparator. Fabricated in 65nm CMOS, the silicon results of the PMOS-input programmable comparator show programmable power consumption and energy efficiency ranging from 2.7 - 4.1μW and 0.22 - 0.5pJ/conv, respectively. Similarly, the input-referred noise can be programmed from 100 - 180μVrms. Additionally, the power (energy efficiency) and input-referred noise can be programmed at any clock cycle, making this design an ideal solution for the two-comparator SAR ADC architecture. Madhan Venkatesh, Gerardo Molina Salgado, Kevin G. McCarthy, Ivan John O'Connell |
ISCAS | 3 |
| 2021 | Developing novel low complexity models using received in-phase and quadrature-phase samples for interference detection and classification in Wireless Sensor Network and GPS edge devicesabstractDespite Wireless Sensor Networks (WSNs) significantly developing over the past decade, these networks, like most wireless networks, remain susceptible to malicious interference and spectrum coexistence. Other vulnerabilities arise as WSN applications adopt open standards and typically resource and energy-constrained commercial-off-the-shelf equipment. Deployments include safety-critical applications such as the internet of things , medical, aerospace and space and deep-sea exploration. To manage safety and privacy requirements across such a diverse wireless landscape, security on wireless edge devices needs improvement while maintaining low complexity. This paper improves wireless edge device security by developing a novel intelligent interference diagnostic framework. Received in-phase (I) and quadrature-phase (Q) samples are exclusively utilized to detect modern, subtle and traditional crude jamming attacks. This I/Q sample utilization inherently enables decentralized decision-making, where the low-order features were extracted in a previous study focused on classifying typical 2.4–2.5 GHz wireless signals. The associated optimal intelligent models are leveraged as the foundation for this paper’s work. Initially, Matlab Monte Carlo simulations investigate the ideal case, which incorporates no hardware limitations, identifies the required data type of signal interactions and motivates a hardware investigation. Software-defined radios (SDRs) collect the required live over-the-air I/Q data and transmit matched signal (ZigBee) and continuous-wave interference in developed ZigBee wireless testbeds . Low complexity supervised machine learning models are developed based exclusively on the low-order features and achieve an average accuracy among the developed models above 98%. The designed methodology involves examining ZigBee over-the-air data for artificial jamming and SDR jamming of ZigBee signals transmitted from SDR and commercial (XBee) sources. This approach expands to a legitimate node classification technique and an overall algorithm for wireless edge device interference diagnostic tools. The investigation includes developing Support Vector Machine , XGBoost and Deep Neural Network (DNN) models, where XGBoost is optimal. Adapting the optimized models to global positioning system signals establishes the transferability of the designed methodology. Implementing the designed approaches on a Raspberry Pi embedded device examines a relatively resource-constrained deployment. The primary contribution is the real experimentally validated interference diagnostic framework that enables independent device operation, as no channel assumptions, network-level information or spectral images are required. Developed models exclusively use I/Q data low-order features and achieve high accuracy and generalization to unseen data. George D. O'Mahony, Kevin G. McCarthy, Philip J. Harris, Colin C. Murphy |
Ad Hoc Networks | 2 |
| 2005 | MOS table models for circuit simulationabstractCompact MOSFET models for circuit simulation face several competing requirements, such as fast execution times, good accuracy and small memory requirements. This paper describes novel interpolation methods for accurate evaluation of MOSFET characteristics in weak, moderate, and strong inversion regions. These methods form the basis of a new table look-up model implemented in SPICE3F5. The table model provides great flexibility in adjustment of the simulation accuracy, speed, and memory consumption by providing a choice of interpolations and data tables. Application of the model to circuit simulation gives very accurate results in dc, transient, and ac analyses. Victor Bourenkov, Kevin G. McCarthy, Alan Mathewson |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 2 |