In this paper, we propose a new architecture for the two-level lossless data compression and decompression algorithm proposed in that combines the PDLZW algorithm and an approximated adaptive Huffman algorithm with dynamic-block exchange (AHDB). In the new architecture, we replace the CAM dictionary set used in the PDLZW algorithm with a CAM-tag-based dictionary set to reduce hardware cost and the CAM-based ordered list used in the AHDB algorithm with a memory inter-reference (MIR) stage realized by using two SRAMs. The resulting architecture is then implemented based on cell-based libraries with both 0.35-mum 2P4M and 0.18-mum 1P6M process technologies, respectively. With the same process technology, the prototyped chip demonstrates the new architecture not only has better performance, at least 33% improvement, but also occupies less area, only about 44%, and consumes less power, about 50%, in comparison with the architecture proposed in . In addition, the maximum data rate can achieve 2 Gbps when realizing in 0.35 mum 2P4M process technology and 4 Gbps when realizing in 0.18-mum 1P6M process technology.

In this paper, we propose a new two-stage hardware architecture that combines the features of both parallel dictionary LZW (PDLZW) and an approximated adaptive Huffman (AH) algorithms. In this architecture, an ordered list instead of the tree-based structure is used in the AH algorithm for speeding up the compression data rate. The resulting architecture shows that it not only outperforms the AH algorithm at the cost of only one-fourth the hardware resource but it is also competitive to the performance of LZW algorithm (compress). In addition, both compression and decompression rates of the proposed architecture are greater than those of the AH algorithm even in the case realized by software.

The N-input multiplexers based on CMOS switches are conventionally designed with the binary-tree structure to simplify the address decoder and obtain a reasonable delay, which estimates the propagation time from data input end to the output end of the multiplexers. However, this design strategy in general takes too much hardware and incurs too much delay. To reduce both delay and cost, some structures other than the binary-tree structure have to be used. Therefore, in this paper we propose a general procedure based on the heterogeneous-tree structure for designing fast large fan-in CMOS multiplexers. The results show that not only can the speed be increased but the cost can also be reduced considerably for the proposed circuits with various input sizes. In addition, we show that both the binary-tree structure and the uniform structure are special cases of the proposed approach.

Up until now the trace back technique and the register-exchange approaches are two major techniques used for the path history management in the chip designs of Viterbi decoders. The former takes up less area but requires much more time than the latter, since it needs to search the trace of the survivor path back sequentially. We propose an alternate approach that is based on the concept of a permutation network and implements directly the trellis diagram of a given convolutional code. Instead of using registers to store the survivor path data, all information is recorded in a permutation network, and the resulting circuit has a smaller routing area than the register-exchange technique and has faster decoding speed than the trace-back method regardless of the constraint length. In addition, it is more straightforward to realize the permutation networks path history unit than the trace-forward unit.

This paper introduces a new concept by which it is possible to design and implement arithmetic processors using permutation networks. To demonstrate this concept, several optoelectronic arithmetic units combining optical directional coupler switches and cyclic permutation networks are designed. The designs show that addition, subtraction, and multiplication can all be performed in O(log n) time in residue code domain and using O(n/sup 2/) directional coupler switches and gates, where n=log M, and M is the integer range of interest. These arithmetic units also have the capability of concurrent error detection and fault-tolerance, and they can be used to construct constant time inner product processors.

Tree and mesh architectures have been considered as two of the most highly scalable parallel multicomputers due to their scalabilities which are superior to those of hypercubes. However, the load balancing on these two multicomputer systems are not as well as we expected. The worst case of tree architecture requires O(M/spl times/p/spl times/logp) routing time for redistributing the workload over the system and it requires O(M/spl times//spl radic/p) for mesh architecture while pipelined packet routing scheme is used. In this paper, we propose an approach based on superconcentrators to reduce the above bounds to O(Mlogp) for both cases with only additional O(p) cost. Furthermore, by using this scheme, the underlying systems can leave the load balancing problem entirely to the superconcentrator so that there does not arise any additional workload of the systems. In addition, this scheme also adds extra communicating paths to the processors so that it not only increases the communication capacity among the processors but also could tolerate edge faults of the systems.

Inner product and matrix operations find extensive use in algebraic computations. In this brief contribution, we introduce a new parallel computation model, called a permutation network processor, to carry out these computations efficiently. Unlike the traditional parallel computer architectures, computations on this model are carried out by composing permutations on permutation networks. We show that the sum of N algebraic numbers on this model can be computed in O(1) time using N processors. We further show that the inner product and matrix multiplication can both be computed on this model in O(1) time at the cost of O(N) and O(N/sup 3/), respectively, for N element vectors, and N/spl times/N matrices. These results compare well with the time and cost complexities of other high level parallel computer models such as PRAM and CRCW PRAM.>

Conventional fault-tolerant modulo arithmetic processors rely on the properties of a residue number system with L redundant moduli to detect up to L/2 errors. In this paper, we propose a new scheme that combines r-out-of-s residue codes with Berger codes to concurrently detect any number of module errors without any redundant moduli. In addition, this scheme can tolerate L faults if L redundant moduli are used, and has the property of graceful degradation when the number of faulty moduli exceeds L. Finally, it is shown that the added cost for fault tolerance is much less than those were reported earlier in the literature.>