The power integrity of high-speed interfaces is an increasingly important issue in mobile memory systems. However, because of complicated design variations such as adjacent VDD domain coupling, conventional case-specific modeling is limited in analyzing trends in results from parametric variations. Moreover, conventional industrial methods can be simulated only after the design layout is completed and it requires a lot of back-annotation processes, which result in delayed delays time to market. In this paper, we propose a chip-package-PCB coanalysis methodology applied to our multi-domain high-speed memory system model with a current generation method. Our proposed parametric simulation model can analyze the tendency of power integrity results from variable sweeps and Monte Carlo simulations, and it shows a significantly reduced runtime compared to the conventional EDA methodology under JEDEC LPPDR4 environment.

Among power dissipation components, leakage power has become more dominant with each successive technology node. Power-gating techniques have been widely used to reduce the standby leakage energy. In this work, we investigate a power-gating strategy for through-silicon via (TSV)-based 3D IC stacking structures. Power-gating control is becoming more complicated as more dies are stacked. We combine the on-chip PDN and TSV in a multilayered 3D IC to perform power-gating analysis of the static and dynamic voltage drops and in-rush current. Then, we propose a novel power-gating strategy that optimizes the in-rush current profile, subject to the voltage-drop constraints. Our power-gating strategy provides a minimal wake-up latency such that the voltage noise safety margins are not violated. In addition, the layer dependency of the 3D IC on the power gating is analyzed in terms of the wake-up time reduction. We achieve an average wake-up time reduction of 43% for all cases with our adaptive power-gating method that exploits location (or layer) information regarding the aggressors in a 3D IC. A tapered TSV architecture based on the layer dependency has been analyzed; it exhibits up to 18% wake-up time reduction compared to that of circuits with uniform TSVs.

For the successful electrical design of system-in-package, this paper proposes an efficient method for extracting wideband resistance and inductance from a large number of 3-D interconnections. The proposed method uses the modal equivalent network from the electric field integral equation with cylindrical conduction-mode basis function, which reduces the matrix size for large 3-D interconnection problems. Additional enhancement schemes proposed further reduce the cost for computing the partial inductances. Therefore, the method discussed in this paper can be used to construct accurate models of a large number of 3-D interconnection structures such as more than 100 bonding wires used for stacking chips.

For the modeling of interconnect in three-dimensional packagings, this paper proposes a method based on the electric field integral equation (EFIE) with cylindrical conduction mode basis functions (CMBF). The bases are defined to describe arbitrary skin and proximity effects, and partial impedances are obtained from the formulation of the EFIE with CMBF's. Examples of several 3-D interconnects verify that the proposed method is efficient in speed and memory.