International audience

The European FAMES Pilot Line addresses a set of technologies including fully depleted silicon-on-insulator technology advanced nodes and embedded non-volatile memories. This paper addresses these two technologies and the programs planned to help designers to use these technologies at their best. The specific electrical properties of FD-SOI devices, are discussed, both in terms of transistor modelling and process highlighting the levers exploited to boost the performance of the future 10-7nm nodes will be also highlighted. The paper also address embedded Non-Volatile Memory (eNVM) devices integrated in the BEOL of advanced FD-SOI CMOS technologies with the aim to open opportunities for disruptive IC architectures and designs using the most appropriate eNVM for the considered applications. OxRAM, FeRAM, BEOL FeFET and MRAM are addressed in FAMES and in the paper and potential new applications are discussed. Finally, the way these technologies are provided to designers through training programs is described.

Physically Unclonable Functions (PUFs) have emerged as a promising hardware-based solution that leverages inherent process variations during IC manufacturing for secure key generation and device authentication, by generating unique and irreproducible challenge-response pairs (CRPs). Among various PUF designs, arbiter PUFs are particularly attractive due to their simplicity, scalability, and compatibility with lightweight cryptographic systems. However, their resistance to fault injection attacks remains an underexplored area. In this work, we investigate the impact of pulsed ElectroMagnetic (EM) fault injection (FI) on a novel Time Measurement-based Arbiter-PUF (TMAPUF) implemented on an FPGA. Experimental results reveal that a single precisely tuned EM pulse can consistently alter the PUF’s output, exposing a critical security weakness. This finding highlight the need for improved fault resilience in PUF architectures and suggest that the studied PUF variant could serve as a foundation for developing inherent countermeasures against EMFI and similar fault-based attacks.

Designing a reliable and lightweight Physical Unclonable Function (PUF) is of prior importance in the context of hardware security. In this paper, a new variant of an arbiter PUF is proposed. Unlike the classical arbiter PUF that only compares the delay of two symmetrical paths, we propose to measure the path propagation delays and returns the time difference. Such measurements enable the arbiter PUF to be used in conjunction with techniques such as filtering of unreliable or low-entropy challenges and, thus, improve the global PUF performances. This ability is obtained thanks to an asynchronous Time-To-Digital Converter (TDC), which allows the measurements of the path delays. The proposed PUF benefits from the strengths of a classical arbiter PUF, such as the ability to extract a large number of challenge-response pairs at high throughput while improving reliability and entropy. This new arbiter PUF has been implemented on an FPGA and the results show it can achieve almost ideal values for metrics such as uniqueness, reliability and uniformity, simply by filtering the most unreliable responses.

This paper proposes an FPGA implementation of Self-Rimed Ring Oscillator (STRO) based Time-to-Digital Converter (TDC). Thanks to the STRO features, this TDC is able to achieve a time resolution as fine as needed by simply increasing its number of stages. Even if the achievable time resolution is close to the tenths of picoseconds, the approach does not require a high frequency oscillator. This resolution is only limited by the STRO-stage noise in the FPGA. As a hardware proof-of-concept, this TDC has been implemented in a Cyclone IV FPGA to further confirm and evaluate the advantages of our proposed TDC architecture. Most of the measurements are perfectly in accordance with our theoretical claims.

This paper presents a novel methodology to enhance harmonic rejection in N-Path Mixers thanks to a dedicated switch control law. The proposed method reduces the effective local oscillator distortion, in order to limit unwanted harmonics appearance at the mixer output. This is achieved by using a non-conventional control of the N-path mixer switches, based on level crossing sampling techniques. The methodology strength is its ability to be used with any N-path mixer, whatever the number of paths. The article details how to optimally design the switch control. To validate the effectiveness of the proposed approach, simulations have been conducted on 4-path and 8-path mixers and compared to the corresponding conventional N-path mixers. This analysis shows significant improvements in terms of harmonic rejection thanks to this new methodology.

In this study, a harmonic-rejection N-path mixer is designed, implemented, calibrated, and measured. The proposed mixer features a wide bandwidth suitable for low-power multi-standard RF front-end receivers while keeping low complexity by opting for only 5 paths rather than 10 and only one stage to perform harmonic rejection up to the$7^{th}$local oscillator (LO) harmonic. This work employs a calibration strategy to prevent mismatches due to the fabrication process from affecting the system performance. The 0.17-1.2-GHz RF front-end mixer is fabricated in a 28-nm FDSOI technology. Measurements show a harmonic rejection higher than 45 dB for the$3^{rd}$,$5^{th}$, and$7^{th}$LO harmonics, 13 dB gain, 13.3 dB NF, −3.5 dBm in-band IIP3. The total power consumption is only 22 mW for a surface area of$0.62\times 0.22~mm^{2}$.

This paper presents new kinds of image sensors based on TFS (Time to First Spike) pixels and DVS (Dynamic Vision Sensor) pixels, which take advantage of non-uniform sampling and redundancy suppression to reduce the data throughput. The DVS pixels only detect a luminance variation, while TFS pixels quantized luminance by measuring the required time to cross a threshold. Such image sensors output requests through an Address Event Representation (AER), which helps to reduce the data stream The resulting event bitstream is composed by time, position, polarity, and magnitude information. Such a bitstream offers new possibilities for image processing such as event-by-event object tracking. In particular, we propose some processing to cluster events, filter noise and extract other useful features, such as a velocity estimation.

Asynchronous Micropipeline circuits are an effective alternative to their synchronous counterparts for reducing dynamic power consumption because they offer proper signaling for disabling useless blocks. In this paper, a novel approach is suggested that uses such signaling to prune irrelevant data. The result is a decrease in the switching activity and an increase of the average throughput, making the circuit more power efficient. The method relies on new control-path elements, which conditionally prune data-path elements. Thanks to these controllers, the registers do not sample new data when pruned and subsequent data propagation is avoided. The former are able to replace any standard controllers in Micropipeline circuits without changing the architecture of the control-path. Furthermore, the outline of the methodology is given for a Micropipeline circuit and is explained through an illustrative example.

Fully Depleted Silicon on Insulator (FDSOI) technologies offer new possibilities for power management, especially with dynamic body biasing. Traditional strategies are based on a large body bias generator, which drives the IP back-gates thanks to a dedicated and often complex power management system. As asynchronous circuits use local synchronizations with handshake components, which activate only the processing parts, it is possible to take advantage of these handshake signals to implement a simple and fine-grain body biasing strategy. Instead of driving IPs with a large body bias generator, we use tiny distributed generators, locally activating small body bias regions when the circuit is processing data. These latter are based on level-shifters and implemented as standard cells. Thus, we propose a high-level design flow associating asynchronous circuits and a local body biasing strategy, which does not require complex body bias management. Indeed, the local handshake signals directly control our dedicated body bias generators. Moreover, Place and Route operations are facilitated by the use of standard cell generators. The simulations show the flow efficiency, a finer grain body biasing and a significant power reduction.

At-speed testing for asynchronous circuits is still an open concern in the literature. Due to its timing constraints between control and data paths, Design for Testability (DfT) methodologies must test both control and data paths at the same time in order to guarantee the circuit correctness. As Process Voltage Temperature (PVT) variations significantly impact circuit design in newer CMOS technologies and low-power techniques such as voltage scaling, the timing constraints between control and data paths must be tested after fabrication not only under nominal conditions but through a range of operating conditions. However, this requirement demands modifications in the control and data paths, which are not straightforward and not desirable from a commercial standpoint due to its incompatibility with conventional testing tools. Even with the available testing methodologies for asynchronous circuits in the literature - by adapting the existing techniques for synchronous or creating new ones from scratch - those methodologies usually target the control or data path. This work explores an at-speed testing approach for bundled data circuits, targeting the micropipeline template. The main target of this test approach focuses on whether the sized delay lines in control paths respect the local timing assumptions of the data paths. By adding extra controllability points in the controllers and taking advantage of scan-chain structures, this work targets to generate/stall tokens in controllers, enabling circuit verification through available scan chains.

The fast evolving pace of electronic mobile devices have made mandatory to reduce power consumption without compromising the circuit performance or its robustness. Asynchronous circuits have demonstrated to be an excellent solution to help designing robust and energy-efficient circuits required for the Internet-of-Things and the mobile applications. Their local synchronization mechanisms, based on handshake protocols, make them perfectly suitable for exploiting dynamic power management techniques, such as Adaptive Body Biasing (ABB) in FD-SOI technologies. Indeed, the circuit activity is simply detected by using the already existing handshake signals, enabling the application of different ABB strategies with almost no modification to the original asynchronous circuit. As the synchronization mechanisms are local to small logic blocks, the ABB strategy is able to target from small to large body bias domains. In order to manage such a technique, an analog dedicated standard cell has been designed to body bias small regions. Depending on the body bias domain granularity, an appropriated number of these specific cells is inserted exactly as logic standard cells during the back-end operations. Additionally, the robustness of asynchronous circuits makes possible changing the transistor threshold voltage on-the-fly, a requirement for applying ABB schemes without complex power management issues.

This paper presents a full digital ASK demodulation technique, targeting the usage of advanced technology nodes. Matlab simulations validate the functionality of the demodulator. The whole structure of this method uses two hysteresis comparators, one custom voltage level generator, two logical gates, a small delay block and a register. This technique allows a minimum modulation index of 3%, a SNR of 28 dB and a bitrate of fc/4. When using higher MI values, the method is more sensitive and resistant to noise, reaching for example a BER = 0.15%, with a MI = 30% and a SNR = 13 dB.

Asynchronous circuits, as any IC, are vulnerable to hardware Trojans (HTs), which might be maliciously implanted in IC designs during outsourced fabrication phases. In this paper, a new testing technique to detect HTs by exploiting the regular side-channel properties of quasi-delay insensitive (QDI) asynchronous circuits is proposed. The technique does not need neither additional circuitry nor significant adjustments in the post-fabrication testing phase. Simulation results show that the proposed technique is able to detect HTs with dimensions smaller than 1% of the original circuit.

Dynamically scaling down the voltage of integrated systems is an effective technique for enabling low-power operation modes. The system is partitioned into several subcircuits, and inactive parts are dynamically biased with low voltages. Additionally, controlling the body bias of subcircuits allows modifying transistor threshold voltages for optimizing speed and power. Both these techniques shift voltages to different levels, demanding dedicated level shifter cells. This paper presents a novel level shifter CMOS architecture able to operate with ultra-low voltages at the expense of reasonable delay and power penalty. Results in technology UTBB FD-SOI 28 nm show the proposed architecture would be controllable by subcircuits of systems operating at 0.19 V, which is lower than the minimum voltage (0.32 V) reachable by the most effective state-of-the-art level shifter cell simulated under the same conditions.

Meeting the requirements of low-power design is a real challenge in the semiconductor industry. In the past few years, many new methodologies have been introduced to help engineers dealing with the growing complexity of chip design. One of such methodologies is the power-intent description based on the Unified Power Format (UPF), which defines, for the first time, a structured standard language to annotate power-intent to a design. This work aims to further improve the deployment of UPF standard in the industry, proposing a methodology that enables design editing and manipulation with automatic detection of power-intent inconsistencies. This work demonstrates how to highly correlate the UPF and Hardware Description Language (HDL) in order to track power-intent inconsistencies due to modifications in either of the descriptions. The final goal will be to offer in the long term a completely automated tool which captures the changes in HDL code and modifies the UPF accordingly (and vice-versa). A test-case is presented to illustrate the capabilities of the developed design methodology.

Seeking low-power consumption high-performance embedded systems has been at the center of interest for researchers around the world for the last decades, especially with the recent boom of different hand-held battery-operated mobile connected devices. The new trends and needs of faster, smarter and smaller internet connected systems, also known as the IoT, require developing very-low power embedded systems including actuators, sensors and signal processors. In this paper, we focus on the architecture optimization efforts to reduce the required activity using the FIR filter as a demonstration example. The new optimized implementation of the FIR filter was compared with other synchronous and asynchronous FIR filter versions realized using the ALPS framework developed at TIMA laboratory. The obtained FIR architecture exhibits 43% less area and up to 61% power consumption reduction compared to the best previous synchronous implementation. We plan to use these results to improve the automatically generated datapath of the high-level synthesis tool of our framework (ALPS-HLS).

Today, high performance and low power consumption are important requirements for the embedded SoCs. The variation in transistors characteristics is increasing as CMOS transistors are scaled to nanometer sizes. Indeed, the MIPS per Watt ratio are more and more an important requirement for digital systems. This makes the power consumption constraint a relevant design criterion. This paper illustrates a new architecture based on an asynchronous approach able to easily reduce the power consumption without performance degradation on an existing design. The evaluation results demonstrate the effectiveness of the proposed technique. This new technique can be considered as generic for systems based on busses or NoCs. Experimentation has been done on the industrial AXI bus.

Many True Random Numbers Generators (TRNG) use jittery clocks generated in ring oscillators as a source of entropy. This is especially the case in Field Programmable Gate Arrays (FPGA), where sources of randomness are very limited. Inverter Ring Oscillators (IRO) are relatively well characterized as entropy sources. However, it is known that they are very sensitive to working conditions. This fact makes them vulnerable to attacks. On the other hand, Self-Timed Rings (STR) are currently considered as a promising solution to generate robust clock signals. Although many studies deal with their temporal behavior and robustness in Application Specific Integrated Circuits (ASIC), equivalent study does not exist for FPGAs. Furthermore, these oscillators were not analyzed and characterized as entropy sources aimed at TRNG design. In this paper, we analyze STRs as entropy sources for TRNGs implemented in FPGAs. Next, we compare STRs and IROs when serving as sources of randomness. We show that STRs represent very interesting alternative to IROs: they are more robust to environmental fluctuations and they exhibit lower extra-device frequency variations.

Monitors are small IPs that check critical systems, such as radio-altimeters that on-line control the landing phase in modern planes. It is essential to get correct information and avoid erroneous messages from these monitors. Asynchronous monitors are very robust to the environment variations; they remain functional in a wide range of power supplies or temperatures, and can reliably monitor synchronous circuits in a harsh environment. This paper discusses how asynchronous monitors can be modeled and generated from Property Specification Language (PSL). These monitors have been implemented and validated on a FPGA board and a CMOS 65 nm technology.

Today signal processing systems uniformly sample analog signals without taking advantage of their intrinsic properties. For instance, temperature, pressure, electrocardiograms, speech signals significantly vary only during short moments. The digitizing system does not take into account this specificity and furthermore is highly constrained by the Shannon theory which fixes the sampling frequency at least twice the input signal frequency bandwidth. It has been proved that Analog-to-digital Converters (ADCs) using a non equi-repartition in time of samples leads to interesting power savings compared to Nyquist ADCs. A new class of ADCs called A-ADCs (for Asynchronous ADCs) based on level-crossing sampling (which produces non-uniform samples in time) and asynchronous technology has been developed. This article will present a fully non-uniform filtering technique associated to such an ADC which is able to drastically reduce the power consumption.

A high-speed multi-phase oscillator based on self-timed ring is proposed. Self-timed rings (STR) are promising approach for designing high-speed serial links and clock generators. Indeed, the architecture of STR allows us to achieve high frequencies with multiphase outputs and their oscillation frequency is not only depending on the number of stages but also on the initial state of the ring. Moreover, this architecture allows us 3 dB phase noise reduction when, while keeping the same frequency, when the stage number is doubled. In this paper, we propose a method to design STR able to generate high-speed multi-phase outputs and we suggest a design flow for designing low-phase noise self-timed ring oscillators. All the electrical simulations and results have been performed using a CMOS 65nm technology from STMicroelectronics.

On-chip digital oscillators are ubiquitous in every communication applications like in RF architectures or intra-chip communication systems. Actually, their integration to the standard CMOS design flow, their ability to generate high-frequency signals, as well as their configurability make them really attractive for designers. However, these kinds of digital oscillators suffer from their sensitivity to any process, voltage, or temperature variations. Self-timed systems are usually considered robust to these kinds of variations. This paper proposes the use of self-timed ring structures for generating high-resolution timing signals. One of the main difficulties when designing such oscillators is to avoid burst oscillating modes and produce uniformly spaced events in order to act as a periodic time-base. Based on a high-level ring model, enriched with stage switching timing information, the temporal behavior of oscillating self-timed rings is studied and their robustness to process variability is evaluated. Several ring architectures are explored to take advantage of complex combination of stages I/Os and it is shown that one can tune a tradeoff between oscillation period and signal stability. In addition, the paper provides designers with the ability to easily prevent burst oscillating modes by applying a very tractable ring design rule. Electrical simulations demonstrate the correctness and efficiency of the approach.

With the growing security needs of applications such as homeland security or banking, the frequent updates in cryptographic standards and the high ASIC costs, the ciphering algorithms on an asynchronous embedded FPGA co-processor are becoming a viable alternative. Within the SAFE project, a novel architecture of asynchronous e-FPGA has been proposed. This architecture is natively robust against side channel attacks such as simple and differential power analysis or clock based fault attacks. Simulation-based security proofs are also presented.

This work is a contribution to enhance the signal processing chain required in mobile systems. The system must be low power as it is powered by a battery. Thus a signal driven sampling scheme based on level crossing is employed, adapting the sampling rate and so the system activity by following the input signal variations. In order to filter the non-uniformly sampled signal obtained at the output of this sampling scheme a new adaptive rate FIR filtering approach is devised. The idea is to combine the features of both uniform and nonuniform signal processing tools to achieve a smart online filtering process. The computational complexity of the proposed approach is deduced and compared to one of the classical FIR filtering approach. It promises a significant gain of the computational efficiency and hence of the processing power.

The integrated systems today require flexibility, performance and reconfigurability. The trends in this domain lead to integrate on a single chip different processing cores, communication units and reconfigurable logic. Therefore the systems-on-chip (SoC) can embed programmable logic. In order to challenge the reconfigurability paradigm for special issues such as communication, synchronization or security, the asynchronous logic is a very promising approach. Nevertheless, the standard programmable logic blocks are not well-suited to map asynchronous circuits. The goal of this study is to define a more adequate programmable structure to implement asynchronous designs on SoCs embedding a reconfigurable part. This work is part of a larger project which includes the design of an embedded programmable logic device (e-PLD) dedicated to the implementation of clockless circuits. The more robust and reliable asynchronous circuits are quasi-delay insensitive. These circuits are mainly constructed with Muller gates. The paper presents a new look-up table (LUT) architecture well-adapted to the Muller gate implementation. This new LUT allows the combination of a single memory-point with combinational logic. This programmable memory is realized thanks to an optional feedback structure. This architecture has been evaluated in CMOS, pass-transistor logic and 3-state logic which is a non-conventional way to design LUTs. The simulations report detailed comparisons between the different logic styles and demonstrate for equivalent power consumption a higher speed for 3-state logic

This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture, dedicated to asynchronous logic, and the logic style. The innovative aspects of the architecture are described. Moreover, the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions, thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.

This paper presents a novel programmable logic device (PLD) architecture for implementing and prototyping various styles of clockless or asynchronous circuits. Many classes of asynchronous circuits exist, depending on the timing assumptions that are made at the logical level and the adopted handshake communication protocols. The main objective of this work is to break the dependency between the PLD architecture dedicated to asynchronous logic and the logic style. Indeed, the PLDs dedicated to asynchronous logic are always style-oriented. The innovative aspects of this architecture are described in details. Moreover, the structure is well suited to be adapted with further asynchronous logic evolutions thanks to the architecture genericity. The programmable structure is flexible enough to be used with different logic styles and asynchronous design flows. As an example, a full-adder was implemented in two different styles of logic to demonstrate the PLD architecture flexibility. This work is included in a larger project called TAST, dedicated to the synthesis and the prototyping of multistyle logic asynchronous circuits.

This paper presents an innovating methodology for network-centric globally-asynchronous locally-synchronous (GALS) system prototyping. High-performance multiclock FPGAs are exploited for easy and fast prototyping of GALS systems based of an asynchronous network-on-chip (ANoC) interfacing synchronous standard IP cores. Modularity property of asynchronous circuits is fully exploited to design regular distributed interconnect topologies by the means of basic topology-free building blocks, with a focus and special design effort to solve arbitration and synchronization problems. A case-study is implemented on an up-to-date FPGA which includes two independently clocked processors, memory banks, serial and parallel communication links and an asynchronous DES (data encryption standard) module connected through an asynchronous 5/spl times/5 crossbar. The clock-less modules are implemented using a quasidelay insensitive logic on the FPGA by the means of a dedicated library. Performance figures are reported on the FPGA platform, especially for communication costs, speed and latency of the ANoC.

Summary form only given. This work presents the design of complex arbitration modules, like those required in SoC communication systems. Clock-less, delay-insensitive arbiters are studied from the perspective of making easier and more practical the design of future GALS or GALA SoCs. This work focuses on high-level modeling and delay-insensitive implementations of low-power and reliable fixed and dynamic priority arbiters.