In the original near-sensor image processing (NSIP) concept, the intensity level for an individual sensor element is mapped onto the time axis so that the time to reach the threshold is inversely proportional to the intensity. In many cases this is favorable, in some cases there is a need for another mapping between time and intensity. We show that such mappings can be achieved by either inserting delays or by varying the threshold voltage. The result is that to achieve a linear mapping it is much more favorable to use a variable threshold since the processing power of the sensor is then better utilized. An interesting result, when it comes to adaptive mapping, is that the traditionally time consuming operation histogram equalization can be accomplished almost for free in the NSIP concept. We also show that other histogram-based, i.e., data-dependent, mapping can be easily implemented.

Today, it is accepted to say that the more bits you have got in your micro processor the better performance you will have. This is probably true if only the performance is concerned. However, if the chip size of the processor is taken into account this might not be the case. In massively parallel architecture, chip area is an important figure. This is especially true for air-borne and, to certain extend, industrial real-time applications. In this paper we study the impact of multi bit processors on the linear SIMD array called RVIP which is an architecture used for real-time radar signal processing. In RVIP, each processing element is bit serial. The results show that the gain in using multi bit processors is very little and that the optimal bit number probably is one or two. We believe that the results from this study can be transferred to other similar systems.

Near-sensor image processing (NSIP) is a new approach to low-level image processing in which the ability to perform global operations is crucial. We define a 2-D global logic unit (GLU), which consists of simple logical circuits arranged in a regular net, and describe how to perform powerful segmentation and feature-extracting operations using this net. Typical segmentation operations performed by the net are hole filling, smallest circumscribing rectangle, thresholding with hysteresis, and arbitrary propagation patterns. We describe how to obtain features like the position of an object in the image. Finally, we show that the NSIP concept, including the global functions, can be implemented in a single chip using today's VLSI technology.

The near-sensor image processing concept, which has earlier been theoretically described, is here verified with an implementation. The NSIP describes a method to implement a two-dimensional (2-D) image sensor array with processing capacity in every pixel. Traditionally, there is a contradiction between high spatial resolution and complex processor elements, In the NSIP concept we have a nondestructive photodiode readout and we can thereby process binary images without loosing gray-scale information. The global image processing is handled by an asynchronous Global Logical Unit. These two features makes it possible to have efficient image processing in a small processor element. Electrical problems such as power consumption and fixed pattern noise are solved. All design is aimed at a 128/spl times/128 pixels NSIP in a 0.8 /spl mu/m double-metal single-poly CMOS process. We have fabricated and measured a 32/spl times/32 pixels NSIP. We also give examples of image processing tasks such as gradient and maximum detection, histogram equalization, and thresholding with hysteresis. In the NSIP concept automatic light adaptivity within a 160 dB range is possible.

Image processing is used in the forest products industry to detect various defects on wood surfaces. Normally, several different sensors are needed, which makes the systems complicated and expensive. In this paper we present a highly integrated sensor system for wood defect detection based on a single MAPP2200 smart sensor. Five different measuring principles are simultaneously utilized to detect surface grayscale, surface roughness, deviating grain direction, 3D-profile and surface density. Using a pixel resolution of 1/spl times/0.5 mm, the sensor permits scanning of boards at the speed of several meters per second.

The paper introduces the concept of near-sensor image processing. By this, the authors mean techniques in which the physical properties of the image sensor itself is utilized to do part of the signal processing task. It is shown that the analog-temporal behavior of photodiodes combined with thresholding amplifiers can be used favorably to do certain low-level image processing tasks including median filtering and convolution. The given examples also show how adaptivity to different light levels can be achieved in a natural way. To extract features from the image, such as moments and shape factors, the authors introduce a simple measurement function.

The PASIC prototype chip contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-bit shift registers, 256 bit-serial processors, and a 256*256 bit dynamic RAM. It appears to be a viable architecture for low-level vision processing. The processors operate in SIMD model at 20 MHz. To avoid high speed transfer of analog data, an A/D converter in the form of a linear array of comparators is used. The architecture of the processing part conforms to the row parallel output from the A/D-converters. A simple but efficient processor excellently suited to the special VLSI constraints of the sensor was designed. The pitch in the present version of PASIC is 30 mu m and it was possible to fit the A/D-converter circuitry, the shift register, the ALU, and the memory into this narrow slot. A key factor is the unified structure achieved by extending the memory data bus to all other units within the same column. The versatility of the chip is shown using three algorithms: edge detection, shading correction, and histogram-based thresholding. Each is executed in approximately 10 ms.>

The processor, A/D converter, sensor integrated circuit (PASIC) prototype chip, which contains 256*256 photosensors, a linear array of 256 A/D converters, two 256 8-b shift registers a 256-bit-serial arithmetic logic unit, and a 256*128-b-dynamic RAM, is presented. It is claimed to be a viable architecture for low-level vision processing. The processors operate in single-instruction multiple-data (SIMD) mode at 20 MHz. When executing an edge-detection algorithm, it is shown that the 256 processors are capable of an output rate of 3 Mpixel/s.>