Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. In this article, we present a hierarchical variance analysis methodology for multistage analog circuits. Starting from the process/layout level, we derive implicit hierarchical relations and extract the sensitivity information analytically. We make use of previously computed values whenever possible so as to reduce computational time. The proposed approach is particularly geared for the domain of design and test automation, where multiple runs on slightly different circuits are necessary. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Circuit and test yield information provides essential feedback to circuit designers and test engineers to evaluate their designs and test set-ups. Traditionally, Monte Carlo analysis and other sample-and-simulate based approaches have been used for yield estimation. However, such computationally costly techniques cannot be used if yield estimation needs to be repeated multiple times, as in the case of test evaluation. In this paper, we propose a technique to conduct accurate and efficient overall yield estimation based on hybrid quadratic modelling and hierarchical statistical profiling. We also develop compatible models for environmental noise and measurement error, two most important error sources in the test process. Our experiments on a baseband amplifier and a cascaded LNA-mixer circuit confirm that the proposed yield estimation technique achieves significant computational time saving with negligible accuracy loss when used for multiple test set-up evaluations.

Due to process variability which makes the analog circuit response probabilistic, fault simulation effectively requires a statistical analysis for each fault. As a result, fault simulation presents the major computational time component in analog test automation. While recently a number of statistical analysis approaches for analog circuits have been proposed, overall computational time is a big concern when a high number of parametric faults need to be evaluated. We present a series of schemes to increase the efficiency of fault simulation by extracting and reusing information from one fault simulation to another. Experiments on a baseband amplifier circuit confirm that the proposed techniques can be collectively applied to provide about a 50-fold simulation time saving at the cost of less than 3% loss in accuracy when compared with similar prior techniques.

The test development efforts for analog circuits today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement setup requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric and catastrophic faults into the circuit and analyzing the masking effect of process variations, we develop a fault injection and simulation technique for analog circuits that is specifically geared toward information reuse. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on several circuits confirm the high accuracy of our variance analysis technique and show a nearly 72% reduction in the number of tests for a three-stage amplifier circuit in the experiment after the application of the test selection algorithm.

In this paper, we present a parametric fault diagnosis approach for analog/RF circuits based on a Bayesian framework. The Bayesian fault diagnosis requires extensive statistical profiling which is enabled by a an efficient hierarchical process variability analysis. Both DC and AC parameters are used as measurements to provide maximum diagnostic resolution. A sensitivity guided test input selection scheme is used to determine the measurement attributes that are most likely to distinguish among the faults. Fault dictionaries are constructed using parametric faults at the transistor level that have both marginal and higher deviations. During the diagnosis step, additional online profiling helps increase the diagnostic resolution. Experiments on a transistor level amplifier circuit confirms that the approach is accurate in terms of statistical attributes and most deviations in layout and process level parameters can be correctly diagnosed.

High-frequency linear analog circuits are widely used in high-speed and wireless radio frequency communication circuits as front-end devices. The small-signal model of transistors is typically used to evaluate the bandwidth (BW) of such devices during design iterations. However, since such devices typically push the boundaries of the manufacturing processes, small-signal parameters are not entirely reliable, leading to systematic silicon failures due to inadequate BW. With increasing uncertainties in the modeling and processing of semiconductor devices, it is essential that the sources of BW failures be identified immediately once the devices are manufactured. This paper presents a methodology to diagnose the systematic BW failures in linear broadband analog circuits. The most important small-signal parameters of internal transistors are determined to enable the redesign process. An evolutionary algorithm specifically designed to mimic the expected errors is used to ensure fast convergence to the correct solution. Sensitivity analysis is used to determine the set of the most impactful small-signal parameters and to guide the evolutionary search. A weighed average approach is also used to improve the accuracy for large-scale systems. Experimental results indicate that the proposed algorithm determines the parameters accurately and scales well in terms of accuracy and computation time

Increasing process variability necessitates reliable analysis of its effects on circuit performance not only at the top level but also at intermediate levels. Mixed-signal circuits with multiple hierarchical layers, multiple parameters, and complex functional relations are especially susceptible to such variations. In this paper, we present a hierarchical method for process variation analysis. The ability to compute the variance of parameters at each hierarchical layer makes the method particularly suited for helping designers through design iterations. Experimental results indicate that the proposed method achieves high computational efficiency with up to 2% compromise in accuracy even for highly non-linear functional relations.

Process variations play an increasingly important role on the success of analog circuits. State-of-the-art analog circuits are based on complex architectures and contain many hierarchical layers and parameters. Knowledge of the parameter variances and their contribution patterns is crucial for a successful design process. This information is valuable to find solutions for many problems in design, design automation, testing, and fault tolerance. We present a hierarchical variance analysis methodology for analog circuits. In the proposed method, we make use of previously computed values whenever possible so as to reduce computational time. Experimental results indicate that the proposed method provides both accuracy and computational efficiency when compared with prior approaches.

Many SOCs today contain both digital and analog embedded cores. Even though the test cost for such mixed-signal SOCs is significantly higher than that for digital SOCs, most prior research in this area has focused exclusively on digital cores. We propose a low-cost test development methodology for mixed-signal SOCs that allows the analog and digital cores to be tested in a unified manner, thereby minimizing the overall test cost. The analog cores in the SOC are wrapped such that they can be accessed using a digital test access mechanism (TAM). We evaluate the impact of the use of analog test wrappers on area overhead and test time. To reduce area overhead, we present an analog test wrapper optimization technique, which is then combined with TAM optimization in a cost-oriented heuristic approach for test scheduling. We also demonstrate the feasibility of using analog wrappers by presenting transistor-level simulations for an analog wrapper and a representative core. We present experimental results on test scheduling for an ITC'02 benchmark SOC that has been augmented with five analog cores.

The test development efforts for analog/RF circuits in computer systems today are disproportionately high due to the lack of widely accepted automation methods. The evaluation of a particular test input and measurement set-up requires the determination of the probabilistic detection of all faults in the circuit. This evaluation step is the most time consuming step during analog test development. Based on the observation that test evaluation requires injecting many parametric deviations into the circuit and analyzing the masking effect of process variations, we develop a hierarchical process variability analysis technique for analog/RF circuits that is specifically geared towards information re-use. We also present a heuristic test selection methodology that aims at providing the same coverage level as the full specification measurements while reducing the test time as well as reliance on hard-to-measure parameters. Experimental results on a differential amplifier circuit confirm the high accuracy of our variance analysis technique and show a 57% reduction in the number of tests after the application of the test selection algorithm.

With increasing uncertainties in the modeling and processing of semiconductor devices, it is essential that the sources of failures be identified once the devices are manufactured. We present a methodology to diagnose the problems in broadband amplifiers by determining the most important small signal parameters of the internal transistors. We use an evolutionary algorithm specifically designed to mimic the expected errors to ensure fast convergence to the correct solution. Sensitivity analysis is used to determine the set of the most impactful small signal parameters and to guide the evolutionary search. Experimental results indicate the proposed algorithm determines the parameters accurately and it scales well in terms of accuracy and computation time.