Two critical aspects in IoT are security and resource consumption. Physically Unclonable Functions (PUFs) are hardware security primitives that exploit the inherent manufacturing variations of integrated circuits to generate unique identifiers. Due to their uniqueness and resistance to cloning, they are widely used for IoT device authentication. In this work, a novel approach to enhance the identifiability of compensated measurement PUFs is introduced. This method involves applying specific weight masks to the parameters extracted from the PUF entropy source before conducting comparisons to determine the output bit. This technique has been tested on several types of PUFs constructed using public datasets. As a result, it has been observed that the Equal Error Rate ( EER ) can be greatly improved, up to two orders of magnitude. The main advantage of this technique is that it does not modify the architecture of the compensated measurement PUF (which is interesting for IoT devices, as it does not require extra resources), while it also has proven to be generalizable, i.e., the optimal mask parameters can be found using a small set of devices and, then, generalized to a different bigger set of devices. This way, this proposal contributes to the development of novel authentication schemes for IoT devices, addressing both security and resource efficiency, critical issues in IoT environments. • A novel optimization technique to improve the identifiability of a compensated measurement PUF and its theoretical justification. • The optimization requires only a small subset of devices as a training dataset, enabling generalization to a larger population of devices. • The implementation of this technique and test using different types of PUFs constructed using public databases. • The implementation of one technique which does not require additional hardware resources based on initializing counters to a certain value.

This paper analyses the phase performance of a RX front-end architecture implemented in a 65-nm CMOS process for linear phased arrays at 24 GHz. The front-end is based on an array of LNAs and phase shifters, which can be used in analog and hybrid beamformers. The penalties of the radiation pattern are associated with metrics calculated from the phase performance. PVT variations and mismatch have been included. Results show that the front-end could potentially attain, in spite of PVT variations, a value near the defined by the mismatch.

The most promising solution for implementing future quantum computers is to merge the operation of the control and readout electronics into the cryogenic environment required by qubits by its monolithic integration using nanometer CMOS processes. To achieve this and follow the integrated circuit design flow, it is mandatory to develop accurate simulation models of the operation of CMOS devices in the deep cryogenic regime. This work provides an analysis of the operation of CMOS integrated polysilicon resistors in conditions of large current density, this is, close to their breakdown voltage. The experimental results show that while current increases in the integrated resistors as temperature is brought to the cryogenic regime, the impact of resistor breakdown is drastically reduced and even eliminated at deep cryogenic temperatures. This will allow for further scaling of these devices when used in quantum computing applications.

In this work, we propose a novel strategy to increase the identifiability of any PUF that uses the compensated measuring technique. The proposed strategy consists of applying certain Nonlinear Transformations before performing the comparisons of the parameters extracted from the entropy source to obtain the output bit. With this purpose, we apply this technique to different types of PUFs constructed using public datasets, as well as a PUF implemented by ourselves. The results obtained show a significant improvement in the Inter-HD of the PUF of up to 6 percentage points. Likewise, we also show that for some cases, it is possible to improve identifiability by up to two orders of magnitude.

In this work, a novel Weak Physically Unclonable Function (PUF) suitable for FPGA based on 11-LUT Generalized Galois Ring Oscillators (GenGAROs) has been proposed. The GenGARO-PUF has been implemented in 40 Artix-7 FPGAs and 128-bit sequences have been generated for each device. The proposed PUF presents an average Inter-HD of 49.89 %, an average Intra-HD of 1.68 % and an Equal Error Rate (EER) of 2.71 · 10-15. Our proposal has been compared to other state-of-the-art PUFs as well as with a conventional Ring Oscillator PUF (RO-PUF) implemented in the exact same locations of the FPGA. This analysis shows that the proposed PUF can outperform previously proposed PUFs in terms of EER. Finally, an alternative architecture of the proposal using 3-LUT GenGAROs has been implemented and analyzed, proving that it is possible to maintain a high identifiability (EER=6.43 · 10-14) using considerably fewer resources of the FPGA.

This paper presents the design of a differential quadrature all-pass filter as a quadrature generator for being used in a phase shifter operating at 19.5 GHz, employing 65 nm CMOS technology. Various solutions have been investigated to address errors occurring in the phase and magnitude of I/Q signals at the output of the quadrature all-pass filter when connected to the next stage. The best result is obtained when combining asymmetry of the network with the inclusion of two additional resistive elements, achieving a quadrature error lower than$2.0^{\circ}$and a magnitude error lower than of 0.17 from 17 GHz to 22 GHz at the output of the quadrature all-pass filter. As an application, it has been proven that the RMS phase error at the output of a 5-bit active phase shifter has been decreased from$7.6^{\circ}$to$2.3^{\circ}$.

In this paper the potential of CMOS technology will be applied to the design of a new programmable gain amplifier (PGA), for its use in a phase shifter for an array antenna receiver operating over the 18-27 GHz frequency range. The main blocks that will provide the required phase shift are a quadrature signal generator (QSG) followed by a programable gain amplifier (PGA). In addition, the next stage to the phase shifter, consisting of a power combiner, will be added to the design to achieve a better reproduction of the output signal behavior. The PGA topology uses dummy transistors to keep constant the input and output impedances. The phase shifter is digitally programmable using a 4-bit word. The root mean square error at 24 GHz is 3.5º for the phase and 0.76 dB for the gain.

This paper presents the design of a new phase shifter using 65 nm CMOS technology, for its use in a receiver array of antennas operating at the K band (24 GHz). The desired phase shift is obtained by the operation of two main blocks: a quadrature all-pass filter (QAF) and a voltage gain amplifier (VGA). This topology uses dummy transistors to keep constant the input and output impedances. The phase shifter is digitally programmable using a 4-bit word. The root mean square error at 24 GHz is 3.55º for the phase and 0.78 dB for the gain.

Physically unclonable functions (PUFs) have become an important area of study in the field of hardware security. In this paper we have designed a ring oscillator PUF (RO-PUF) implemented it in FPGA and characterised it using a new concept: second-order compensated measurement by two-bit extraction. The results show that it is possible to use two quality bits to generate the response, thus improving the performance compared to conventional RO-PUFs.

In some encryption systems it is necessary to preserve the format and length of the encrypted data. This kind of encryption is called FPE (Format Preserving Encryption) or DPE (Datatype Preserving Encryption). For example, in the case of PCS (Physical Coding Sublayer) at Gigabit Ethernet optical communications, the 8b10b symbol flow can be encrypted at line rate thanks to a symmetric encryption scheme that must preserve the format and coding properties of 8b10b symbols. In this case, since a high speed data flow needs to be encrypted preserving its format, the usage of an FPE stream cipher could be advantageous. For this purpose, a new keystream generator scheme is proposed in this work. It is based on a secure block cipher working in CTR (Counter) mode whose output is subjected to a modulo operation. Moreover, a security analysis for this mode is carried out, deriving an expression for the IND-CPA (Indistinguishability under Chosen Plaintext Attack) advantage of any adversary, concluding that this mode can be considered secure in the same way as traditional modes are. Furthermore, the proposed structure has been implemented over an FPGA (Field Programmable Gate Array) device and adapted to a Gigabit Ethernet application.

This paper presents a didactic strategy based on information and communication technologies (ICTs) to help students build knowledge mental models in the context of Higher Education. It presents a methodology that combines the flipped classroom with other active methodologies and traditional lessons to improve the teaching/learning process of Electronics in university studies in Physics. Using the flipped classroom as the main strategy, the proposed methodology allows devoting more classroom time to active learning so that the instructor can follow the student learning process and evaluate model construction, while at the same time it increases student implication and fosters autonomy and cooperation with peers, contributing to a better construction of knowledge mental models in Electronics.

In this work a new self-synchronized encryption method for 10 Gigabit optical links is proposed and developed. Necessary modifications to introduce this kind of encryption in physical layers based on 64b/66b encoding, such as 10 GBase-R, have been considered. The proposed scheme encrypts directly the 64b/66b blocks by using a symmetric stream cipher based on an FPE (Format Preserving Encryption) block cipher operating in PSCFB (Pipelined Statistical Cipher Feedback) mode. One of the main novelties in this paper is the security analysis done for this mode. For the first time, an expression for the IND-CPA (Indistinguishability under Chosen-Plaintext Attack) advantage of any adversary over this scheme has been derived. Moreover, it has been concluded that this mode can be considered secure in the same way of traditional modes are. In addition, the overall system has been simulated and implemented in an FPGA (Field Programmable Gate Array). An encrypted optical link has been tested with Ethernet data frames, concluding that it is possible to cipher traffic at this level, getting maximum throughput and hiding traffic pattern from passive eavesdroppers.

Information and communication technologies (ICTs) are a privileged instrument to promote and facilitate meaningful student learning. The use of multi-media resources and virtual learning environments has already been adopted in many higher education institutions as part of a mixed learning process. Another tool available for teaching innovation is augmented reality (AR), which allows a combination of digital and physical information in real time using different technological devices. Within the augmented reality, we can find several levels, which start with the 2D codes (QR codes). This work proposes the generation of a set of multi-media resources, accessible by means of QR codes, for the practical sessions in a laboratory of Electronics. With these resources, additional and contextual information is offered, which can be accessed when the student requires it, thus improving the experimental learning process.

A new technique for improving the security of a chaotic cryptosystem has been proposed. An encryption system based on a Skew Tent Map using this technique has been implemented on a Virtex 7 FPGA. The results show that, using this method, the randomness of the sequences can be considerably improved by using a small number of extra resources.

Passive Polyphase Filters (PPF) are extensively used in analog signal processing system which work with quadrature signals, either filtering or generating it. However, the quality of PPF performance in these kinds of operation rely on a perfect matching in components and a symmetrical topology. Thus, mismatch effects could produce notable degradation in PPF response. Despite this, mismatch impact in PPF has not been thoroughly analyzed previously in literature to the best of authors knowledge. In this work, a systematic method is proposed to search the worst possible mismatch in a PPF with any number of stages for a certain tolerance. Then, for the 1-stage case, both PPF types (I and II) are analyzed to evaluate how this non-ideality alters the response of this kind of filters.

In this work a new physical layer encryption method for Ethernet 1000Base-X standard is proposed. The proposed encryption scheme uses a chaotic stream cipher to encrypt the 8b10b symbols flow at PCS (Physical Coding Sublayer) level. The complete system has been implemented in an FPGA (Field Programmable Gate Array). Experimental results are analyzed, concluding that it is possible to cipher traffic at this level and hide the complete Ethernet traffic pattern from any malicious observer. Moreover, no overhead is introduced during encryption and no throughput losses are produced.

A highly-linear low-noise transimpedance amplifier (TIA) with programmable gain for intermediate frequency-over-fiber (IFoF) communications is presented in this paper. It has been fabricated in a 65-nm RF CMOS technology for use in the downlink receiver of remote antenna units for a cost-effective distributed antenna system. The topology consists of a shunt-shunt feedback TIA with open-loop gain control to ensure constant bandwidth, while the transimpedance can be linear-in-dB programmed from 60 to 76 dBO. The IFoF transmission is achieved with a very low error vector magnitude below 2% over an input dynamic range from -16 dBm up to +4 dBm optical power. The TIA shows an equivalent input noise of 8 pA/√Hz at 500 MHz with a bandwidth of 700 MHz. The TIA presents a power consumption of 6 mW from a single supply voltage of 1.2 V, while the total power consumption including the output driver is 19 mW.

In this paper we propose a fast and secure encryption system with a mixed-architecture based on a Modified Logistic Map and a Linear Feedback Shift Register. The system has been simulated showing that it can encrypt and decrypt images efficiently. The encrypted messages have been able to pass the NIST as well as the diehard battery of tests proving that the system is secure.

This paper presents a compact temperature sensor with frequency output, suitable to be used in low-cost wireless sensor networks. It works with a supply voltage of 1.2 V, and a power consumption of 1.35 μW. The sensor, designed in a 0.18-μm CMOS technology using only MOS transistors, shows high linearity over a temperature range of (-40 °C, +120 °C), with output frequencies that vary from 100 kHz. Recovered temperatures show a maximum error of -0.67/+0.66 °C over the whole range.

This paper presents a simple but effective improvement for source coupled logic (SCL) circuits and its application to dual modulus frequency prescaler design. By biasing the standard resistor-load SCL structure with a bias current inversely proportional to the resistor, logic levels are kept over process and temperature variations and, as a result, reliable operation is preserved over a wider range. This technique has been tested in a 1.8 V-0.18 μm CMOS front-end 8/9 prescaler, showing its feasibility for the target 1.35-2.7 GHz input range over all corners and a commercial temperature range of (0, +85oC).

In this paper, we present a new CMOS analog continuous-time linear equalizer. The proposed structure overcomes some of the limitations due to the low supply voltage of the most widely used continuous-time equalizer, the degenerated differential pair. The prototype has been tested for multi-gigabit short-range applications targeting up to 2 Gb/s through a 50-m SI-POF. The proposed linear equalizer was designed in a cost-effective 90-nm CMOS process. The system is fed with a single supply voltage of 1 V and consumes 2.7 mW.

This paper presents an LC-tank-based voltage-controlled oscillator, fabricated in a standard 0.18 μm CMOS technology, with a 44 % tuning range around a center frequency of 1.7 GHz. To minimize the impact of the proposed oscillator on phase noise in phase-locked-loops, it has a coarse control of 27-1 levels, driven by a 7-bit digital word, achieving a tuning sensitivity below 35 MHz/V along the whole tuning range. The oscillator has -123.4 dBc/Hz phase noise at 1 MHz offset and draws 10 mA from a 1.8 V supply, yielding a total power/tuning/frequency-normalized figure of merit equal to -5.5 dB.

This paper presents a new first-order temperature compensated CMOS current reference. To achieve a compact architecture able to operate under low voltage with low power consumption, it is based on a self-biasing beta multiplier current generator. Compensation against temperature is achieved by using instead of an ordinary resistor two triode transistors in parallel, acting as a negative and a positive temperature coefficient resistor, that generate a proportional to absolute temperature and a complementary to absolute temperature current which can be directly added to attain a temperature compensated current. Programmability is included to adjust the temperature coefficient and the reference current magnitude over process variations. Results for a 0.18 μm CMOS implementation show that the proposed 500 nA reference operate with supplies down to 1.2 V accomplishing over a (-40 to +120°C) range temperature drifts below 120 ppm/°C.

A simple and power efficient scheme for input rail-to-rail Op-Amp operation with constant gmand CMRR over the common mode input range is introduced. The input stage uses complementary differential pairs but only one pair is active at a time. Three implementations of the scheme are discussed. They use very compact control circuitry to turn only one of the differential pairs at a time. Simulations and experimental verification of the proposed scheme are provided from a test chip prototype in 0.5μm CMOS technology.

This paper presents a low-voltage CMOS continuous-time adaptive equalizer for short-haul gigabit optical communications. It was designed to compensate the attenuation of a 1.25 Gb/s signal with a simple NRZ modulation, transmitted through a 50-m length 1-mm core step-index plastic optical fiber (SI-POF). The structure includes two adaptation loops to compensate the possible variations in level and spectrum of the input signal. The proposed system was designed in a cost-effective 0.18-µm CMOS process. The system is fed with 1 V and has a total power consumption of 29.3 mW.

A very simple power supply rejection ratio (PSRR) enhancement technique is presented. It is suitable, among others, for low voltage power low power (LVLP) DC circuits such as biasing circuits. It is shown that a high insensitivity to AC noise in supply rails can be achieved with an almost zero contribution to the total internal noise. This is achieved at the expense of very small additional circuitry and no additional power dissipation or supply requirements. Simulation and experimental verification of these characteristics is provided.

This paper presents a high performance 1.2 V-0.18 μm CMOS voltage-to-frequency converter (VFC) that can be used either in single or differential mode. The proposed VFC works over the entire input range with output frequencies ranging between 0.1 and 1.0 MHz. Its operation is ratiometric, with low power consumption (80 μW), allowing its use in battery operated systems. It achieves high linearity (0.015 %) for a temperature range of -40 to +120oC.

A low-voltage high-speed CMOS fully-differential adaptive equalizer based on the spectrum-balancing technique is presented in this paper. It was designed to compensate the strong attenuation of the transmitted signal due to fiber losses. The proposed equalizer, formed by a line equalizer and an adaptation loop, targets 2.5 Gb/s transmission for a simple NRZ modulation through a 50-m SI-POF. It was designed in a 0.18-μm standard CMOS process, fed with 1V and has a power consumption below 17.3 mW.

This paper presents an optical receiver for short reach applications through low-cost plastic optical fiber. The limited bandwidth caused by the fiber and the external photodiode is compensated by a new adaptive equalizer based on the spectrum balancing technique. A clock and data recovery circuit is included that minimizes jitter and metastability using a new multi-level bang-bang architecture. The prototype, implemented in a standard 0.18-μm CMOS process, achieves 1.25 Gb/s with a power under 110 mW at only 1 V.

The operation of bang-bang phase detectors (BBPDs) in clock and data recovery circuits (CDRs) is typically modeled in terms of the phase difference between their inputs; however, this approach is not sufficient to describe their dynamic behavior completely. This paper introduces a more comprehensive model of the operation of BBPDs that takes into account phase as well as frequency differences between their inputs. Numerical simulations of the operation of a CDR have been carried out to evaluate the validity of the model.

This paper presents a new high performance 1.2 V - 0.18 μm CMOS differential voltage-to-frequency converter (dVFC). The proposed dVFC works properly over the whole differential common mode input providing an output frequency range of 0.0 - 0.9 MHz with 0.015% linearity error for a -40 to 120°C temperature range and a 30% supply voltage variation. Power consumption is below 65 μW, which makes it suitable to be used in portable applications.

This paper presents a new analog front-end for short-reach high-speed optical communications. It compensates the limited bandwidth of SI-POF transmission systems. In particular, the front end has been designed using a cost-effective 0.18-µm CMOS technology and fed with only 1V. The proposed architecture, formed by a transimpedance amplifier and a continuous-time equalizer, targets 1.25 Gb/s transmission for a simple NRZ modulation in an optical link composed of 50 m of SI-POF and a large area Si PIN photodetector.

This paper presents an ultra low-power class AB operational amplifier (OpAmp) designed in a low-cost 0.18 μm CMOS technology. Rail-to-rail input operation is achieved by using complementary input pairs with adaptive bias to enhance slew-rate. A class AB output stage is employed. For low-voltage low-power operation, the transistors both in the input and the output stage are biased in the sub-threshold region. The simulated DC open loop gain is 51 dB, the unity gain frequency is 40 kHz with a 65° phase margin and the slew-rate is 0.12 V/μs with 10 pF capacitive loads. A common-mode feed-forward circuit (CMFF) increases CMRR, keeping the DC gain almost constant: its relative error remains below 1 % for a (-40°C, +120°C) temperature range. The proposed OpAmp consumes only 1 μW at 0.8 V supply.

In this paper, a 3.125 GHz four stage voltage controlled ring oscillator is presented. The oscillator has been designed in a 0.18 μm CMOS process with a 1.8 V supply. Behavioural simulations predict an 18% tuning range for the oscillator, with a -91 dBc/Hz phase noise at a 1 MHz offset. Its power consumption has been simulated to be only 12.6 mW.

This paper presents a low-cost CMOS voltage-to-frequency converter (VFC) with almost full-scale input operating range for front-end smart sensor interfaces in wireless sensor networks (WSN) applications. The proposed VFC, designed in a 0.35μm CMOS technology supplied at 3 V, is a cost-effective circuit, exhibiting at the same time high performance characteristics: it operates with a power consumption below 0.8 mW at output frequencies ranging from 0.1 MHz to 2.7 MHz with an error below 4 % given a 0.1-2.7 V input (1 MHz/V sensitivity).

This work introduces a monolithic 10GBase-LX4 limiting amplifier in a low-cost 0.18 µm CMOS digital process intended for optical fiber communications. The proposed configuration includes two inductorless frequency compensated voltage amplifiers. The topology also incorporates a conventional RC network in order to avoid drifts due to matching and temperature between −20 and 80 °C. This circuit presents a 200 kHz lower cut-off frequency and a 3.5 GHz higher cut-off frequency with 32 dB gain.

This paper presents a fast settling compact feedforward automatic gain control (AGC) suitable for use in wireless communication systems such as WLAN or Bluetooth receivers where the use of traditional closed loop feedback amplifiers forms a boundary due to the stringent settling time constraints. The AGC has been implemented in a 0.35 mum standard CMOS technology. Supplied at 1.8 V, it operates with a power consumption of 1.6 mW at frequencies as high as 100 MHz, while its gain ranges from 0 to 18 dB. The settling time of the circuit is below 0.25 mus.

In this paper, a monolithic CMOS optical receiver designed in a 0.18μm digital process suitable for 10GBase-LX4 optical fiber transmissions is described. The system is based on CMOS actively loaded inverter structures and works with a single 1.8 V supply voltage. The thermal effects are minimized between −20 and 80 °C by using two different compensation techniques. The design presents optimized area and power consumption.

In this paper, two adaptive Transimpedance Amplifiers (TIAs) for optical communication receivers are presented and compared. Both TIAs are realized in a low-cost digital 0.35μm CMOS process and fed from a single 1.8V voltage supply. A transimpedance variation range of more than 12dBΩ is attained with an almost constant bandwidth of about 1GHz. The proposed configurations are characterized by their low-power operation and low input-referred spectral noise.

A novel high performance envelope detector is offered in this work. Proposed circuit holds the signal peaks in two periods and combines them to obtain the envelope of the signal. This way, ripple is fixed by the peak holder and tracking can be improved without the traditional compensation between keeping and tracking required in these circuits. A comparison is offered between a conventional circuit, a previous work and the proposed envelope detector. It is shown the superior performance of the latter obtaining small ripple (<1%), fast settling (0.4μs) and high linearity.

This paper presents a new low-voltage pseudo-differential continuous-time CMOS transconductor for wideband applications. The proposed cell is based on a feedforward cancellation of the input common-mode signal and keeps the input common mode voltage constant, while the transconductance is easily tunable through a continuous bias voltage. Linearity is preserved during the tuning process for a moderate range of transconductance values. Simulation results for a 0.35 μm CMOS design show a 1:2 Gmtuning range with an almost constant bandwidth over 600 MHz. Total harmonic distortion figures are below -60 dB over the whole range at 10 MHz up to a 200 μAp-pdifferential output. The proposed cell consumes less than 1.2mW from a single 2.0 V supply.

This paper presents a low-voltage low-power differential programmable gain amplifier (PGA) for wideband applications. The proposed cell is based on a gm-boosted source degenerated differential pair with a hybrid polysilicon-MOS resistor degeneration structure. Fabricated in a 0.35 mum CMOS technology, the PGA consumes less than 0.5 mW at a single 1.8 V supply. Measured results for a 3-bit implementation show a 0 to 18 dB linear-in-dB programmable gain with a constant bandwidth of 100 MHz when driving 150 fF capacitive loads. Distortion levels are below -72 dB over the whole gain range at 10 MHz for a 0.2 Vp-pdifferential output

Sensor nonlinearities, ageing, temperature changes and other physical dependences force to include conditioning circuits in electronic measurement and control systems. This paper shows an analogue-digital processing architecture based on an adaptive circuit designed to extend the linear range of an angular position sensor, compensating the output drift due to temperature variations. System-level simulations give a temperature-independent linear output in the range of 293-353 K, with an accuracy of 2 degrees in the angular position. Inherent low power and low size characteristics make these circuits valuable to implementing the "smartness" part of smart sensors

In this paper we report 2nd and 3rd-order Gm-C filters based on fully-balanced pseudo-differential continuous-time transconductors for applications in low-voltage systems over the VHF range. By using a 0.35 mum standard CMOS process, low-pass filter approximations have been implemented with a cut-off frequency programmability over the 40-200 MHz range, which confirm the feasibility of the proposed strategy in applications such as data storage systems and IF strips. The filters consume less than 4.8 mW per pole at 45 MHz from a 2V supply. The measured dynamic range was better than 53 dB at THD of 1% for all filters. The maximum active chip area is 0.025 mm2per pole

The design, analysis, and system simulation of an adaptive processor based on a current-mode mixed analog-digital circuit is presented. The processor consists of a mixed four-quadrant multiplier and a current conveyor that performs the nonlinearity. Schematics, circuit parameters, and a high-level model are shown. The results achieved when applying this processor model to conditioning several sensor types are discussed.

This paper illustrate the use of a new class of amplifiers known as 'current feedback amplifiers' as the active devices in sinusoidal oscillators. From theoretical analysis, supported by experiments, it is concluded that they offer improved performance, with respect to their opamp based counterparts in terms of frequency accuracy, dynamic range, distortion level and frequency span. At the same time they seem to be more flexible for the inclusion of automatic gain control schemes.>