Non peer reviewed

This special section is composed of substantially extended handpicked papers from the IEEE Nordic Circuits and Systems Conference (NorCAS) 2022 that took place in October 2022 in Oslo, Norway.

This brief presents an approach that dynamically exploits content dependencies in asymmetric memory cells. By using a capacitive, logic-value majority circuit and an extra column of memory cells, words are conditionally flipped during write operations to reach the more beneficial state for storage. A 1-kb SRAM block of low-voltage memory cells was implemented and manufactured in a 130-nm CMOS. The memory cells were made writable and read-stable at low supply voltages with a single-ended write and single-ended read structure using six multithreshold transistors that give rise to an asymmetric retention power. At a supply voltage of 350 mV, the content-dependent leakage power in the asymmetric memory cell is 23 times smaller when storing logic “1”s compared with logic “0”s. A derived statistical model suggests that the mean, wordwise, static power savings of the word-flipping scheme become 15.70% for 8-bit words of uniform bit probability. For the implemented SRAM macro, the mean improvement for the retention power is, including flip logic and decoder and driver overheads, found to be 14.69%. In boundary tests, by writing all words full of undesired values, the power saving becomes 80.37%, while writing all words full of desired values causes a power penalty of 6.14%. Measurement results confirm the improvement in retention power with a ten-chip mean improvement of 11.93% for the same data set.

We present a method to analyze the minimum energy point of subthreshold logic circuits, taking into account the effect of gate sizing and the transistor threshold voltage variability. With respect to a target yield, technology and circuit parameters this method can give estimates of optimal choices for supply voltage and gate sizing, as well as serve as a tool for design space exploration and technology comparision. We apply this modeling technique to a 90 nm technology, and draw contour plots of the design space. These plots indicate that larger than minimum size gates may be required to achieve minimum energy operation in the subthreshold domain. Optimal voltages range from about 350 mV to 550 mV, depending on the switching activity of the circuit. In the appendix we also give a method of approximating the sum of iid. log-normal RVs, which is used to analyze the timing performance of gates in series.

Proton beam characterization was performed at the Oslo Cyclotron Laboratory (OCL) in order to evaluate the beam properties and asses its usability for radiation testing of electronic devices. The characterization was performed with the aim of establishing good guidelines for reliable radiation tolerance testing at the OCL. A dosimetry measurement and calibration setup is proposed as well as a beam-to-target alignment and beam profile measurement setup. The beam characterization was performed using 30 MeV protons.

Multiobjective optimization taking area, power consumption and robustness into account was used to pick two implementations of the minority-3 function as building blocks to implement Muller C-elements. According to our simulations, the generally better among the two implementations was a 12 transistor implementation based on a 10 transistor minority-3 gate, when compared to a 24 transistor implementation based on 2-input nand, 2-input nor and invert functions. For room temperature and a supply voltage of 150mV, the simulated delays for the 12T and 24T implementations were 16.2 µs and 18.5 µs, respectively. The mean static power consumption figures were for the same conditions 2.6pW and 7.4pW, for the 12T and 24T implementations respectively. Switching energy was also simulated for a 150mV supply voltage. The switching energy for the 12T version of the Muller C-element was almost 44% lower compared to the 24T implementation. We also report delay, power and energy for a supply voltage of 300mV.

Low supply voltages, small currents and small circuit feature sizes will for CMOS logic typically coincide with deteriorating robustness, i.e. a reduction of a circuits ability to maintain correct functionality across all operating conditions. In this paper we examine three circuit topologies implementing the minority-3 function, operating at a power supply voltage of 150 mV in a standard 65 nm CMOS process. Using a heuristic multiobjective optimization algorithm we consider each circuits area and metrics for power and robustness, and optimize each circuit to find an approximation to the optimal trade-off surface (a Pareto front) for these objectives.

Two memory elements, or latches, are introduced. They are similar in functionality to widely used NOR- and NAND-based crosscoupled latches, but unlike the traditional latces they do not risk to produce stable states where Q and Q' have identical binary values. The suggested solutions are built from two inverters and one minority-3 gate. Monte Carlo simulations in 90 nm CMOS are used to demonstrate that the circuits may maintain the digital abstraction under mismatch and process variations for a supply voltage down to 140 mV at 20 degrees C and 100 nm gate lengths. Chip measurements are included. Reliability issues for low fan-in threshold gates might favour them over some traditional Boolean implementations, which may contribute to increased use of CMOS threshold gates, if proven.

In this paper several low power full adder topologies are presented. The main idea of these circuits is based on the sense energy recovery full adder (SERF) design and the GDI (gate diffusion input) technique. These subthreshold circuits are employed for ultra low power applications. While the proposed circuits have some area overhead that is negligible, they have at least 62% less power dissipation when compared with existing designs. In this paper, 65 nm standard models are used for simulations.

In this paper, a new, real-time reconfigurable perceptron circuit element is presented. A six-transistor version used as a threshold gate, having a fan-in of three, producing adequate outputs for threshold of T =1, 2 and 3 is demonstrated by chip measurements. Subthreshold operation for supply voltages in the range of 100-350 mV is shown. The circuit performs competitively with a standard static complimentary metal-oxide-semiconductor (CMOS) implementation when maximum speed and energy delay product are taken into account, when used in a ring oscillator. Functionality per transistor is, to our knowledge, the highest reported for a variety of comparable circuits not based on floating gate techniques. Statistical simulations predict probabilities for making working circuits under mismatch and process variations. The simulations, in 120-nm CMOS, also support discussions regarding lower limits to supply voltage and redundancy. A brief discussion on how the circuit may be exploited as a basic building block for future defect tolerant mixed signal circuits, as well as neural networks, exploiting redundancy, is included.

Advancement in silicon technology has led to miniaturization of devices, scaled power supply voltages and faster transistor switching speeds just to name a few. Along with these improvements came issues such as threshold voltage scaling, interconnect delays, sensitivity to variations, and increased power dissipation. Device miniaturization has also seen a rise of battery-operated electronic devices with very stringent energy requirements. Clearly, power dissipation is already a major design challenge in highly integrated systems. Leakage currents are becoming significant as the power supply and threshold voltages are scaled. Low power/energy techniques are thus very critical. This tutorial will review known techniques for reducing power/energy, focusing on recent results scaling the supply and the device threshold voltages and on bridging the divide between strong and weak inversion operations, as well as on using emerging nanoelectronic devices. These will show that GHz frequencies could be sustained in the (sub-)femto Joule per inverter energy range.

This paper presents a novel technique for biasing multifunction CMOS gates operating in the subthreshold region, to achieve better matching between nMOS and pMOS subthreshold currents. Two different implementations of the minority-3 gate have been simulated in a general purpose 90 nm triple-well process. The proposed regulator circuit increases the degree of symmetry between rise and fall times for both gates, compared to the unregulated case where the wells were tied to a fixed voltage. Simulations also show improved stability across a large temperature range for both circuits when use of the regulator is employed. Through Monte-Carlo simulations for typical process parameters it is also shown that low-level redundancy significantly increases yield for both minority-3 gates

In this paper, the authors present pseudo-floating-gate (PFG) binary and analog inverters with feedback control. The PFG inverter can be used to implement digital, multiple-valued (MV) and analog circuits. The PFG inverter will suppress low frequency components due to a local feedback. PFG circuits can be utilized for low voltage (LV) binary-, multiple valued logic and analog circuits. Typical applications are detection of high frequency components in sensory signals, i.e. airbag sensors. A differential LV amplifier is presented. Simulated data is valid for a CMOS process with at threshold voltage equal to 0.4V. The circuits has been implemented in a 130nm CMOS process

This paper explores low power reliable micro-architectures for addition. Power, speed, and reliability (both defect- and fault-tolerance) are important metrics of system design, spanning device, gate, block, and architectural levels. The analysis considers the low power needs of future systems at supply voltages comparable to threshold voltages (V/sub th/). Theoretical analysis and simulations show a decline of the speed advantages of parallel adders when considering wire delays. These evaluations suggest that serial adders might do better for (ultra) low power operation, with redundancy for enhancing reliability. We analyze 32-bit multiplexed serial adders. The robustness when using output-wired mirrored adder (majority) gates is shown under faulty conditions. Simulations (at 180nm, 120 nm, and 70nm) identify the supply voltages where the power-delay and energy-delay products are minimized. These show that redundant serial adders are not only low power and reliable, but can trade speed for power in a wide range (by varying V/sub DD/ both above and below V/sub th/).

We present a new defect/fault tolerant ultra low power CMOS circuit exploiting low level redundancy. We show that wiring and transistors may be damaged while the functionality is still kept. We also demonstrate a new full adder based on the basic building block, capable of sub fJ power-delay-product for supply voltages below 100 mV, in a 120 nm process. The power-delay-product is reduced by about 50 % compared to the best previously published FA based on a 6 transistor reconfigurable subthreshold NOR-3, MAJ-3, NAND-3 circuit. Transistors are exploited as four terminal devices operating in subthreshold and DC characteristics for a threshold element is demonstrated by chip measurements.

We present a reconfigurable linear threshold element which may he used to implement the Boolean functions NOR3, C~A~R~R~Y~) and NAND3. Several of the blocks may be used to implement any Boolean function. Pseudo floating-gate transistors are used in order to set the appropriate threshold.

We present an idea for a new real-time reconfigurable perceptron, also called, a threshold element. The circuit example contain three inverters with shorted outputs. SPICE simulations for a 0.6 /spl mu/m CMOS implementation operating in the subthreshold region. are shown. The threshold voltages of the active devices, seen from driving nodes, may be dynamically changed by adjusting their substrate potentials. This enables a change of the threshold of the perceptron circuit in real-time. In terms of Boolean logic the functionality may be changed between 3-input NOR, CARRY' for the FULL-ADDER function and 3-input NAND, in real-time.

This paper describes using theory, computer simulations, and laboratory measurements a new class of real-time reconfigurable UV-programmable floating-gate (FGUVMOS) linear threshold elements operating with current levels typically in the pA to /spl mu/A range, in standard double-poly 0.6 /spl mu/m CMOS, providing an ultra low-power potential. A new design method based on using the same basic two-MOSFET circuits extensively is proposed, meant for improving the opportunities to make larger FGUVMOS circuitry than previously reported. By using the same basic circuitry extensively, instead of different circuitry for basic digital functions, the goal is to ease UV-programming and test and save circuitry on chip and I-O-pads. Matching of circuitry should also be improved by using this approach. Compact circuitry can be made, reducing wiring and active components compared to previously reported FGUVMOS. 2-MOSFET circuits able to implement CARRY, NOR, NAND, and INVERT functions are demonstrated by measurements on chip, working with power supply voltages ranging from 800 mV down to 93 mV. The basic linear threshold element proposed is considered as a potential basic building block in neural networks.