Delay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program. The program has successfully produced sets of delay tests for large logic networks. The average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal.

The correspondence between Boolean network probabilities and the design formalisms of Ledley and Aiken is demonstrated.

Dynamic self-checking is a technique used in computers to detect a fault quickly before extensive data contamination caused by the fault can occur. When the self-checking properties of the computer circuits are not perfect, as in the case of self-testing only and partially self-checking circuits, a recovery procedure may be required to roll back program execution to a point prior to the first undetected data error caused by the detected fault.

A new technique for low-cost error correction is the alternate-data retry (ADR). Like a conventional retry, an ADR is a re-execution of an operation that initially fails to produce an error-free result. Unlike a conventional retry, an ADR uses an alternate representation of the initial data. The choice of the alternate data representation and the design of the processing circuits combine to insure that even an error due to a permanent fault is not repeated during retry. Error correction is provided at a hardware cost comparable to that of a conventional retry capability.

The sequential and indeterminate behavior of an end-around-carry (EAC) adder is examined. This behavior is commonly overlooked in the literature. Design modifications to impose determinism are provided. These modifications also eliminate the troublesome negative zero found in the one's complement number system.