Algorithms for parallel execution of forward elimination to solve linear equations arising from very large scale integrated circuit simulation are discussed. Here, a multigranular method is introduced, exploiting different levels of potential parallelism. According to these levels, the new method contains four phases, which are dynamically linked. Therefore, the use of an architecture with shared memory in connection with multithreaded programming enables the parallelization of a serial well-adapted sparse-matrix solver. In order to take system-specific properties into account, an adaptive partitioning is proposed. For this, the partition size is enlarged step by step as long as the measured execution time decreases. Applying this method to industrial examples an efficiency of processor usage of nearly 90%, with up to 12 processors, is reached for relevant circuits.

In most cases steady-state semiconductor device equations are solved simultaneously by Newton's method, by Gummel's decoupled nonlinear relaxation scheme, or a combination of both. A framework deriving such different iterative methods from underlying variable transformations is presented. Within that framework the introduction of a new variable establishes a new nonlinear relaxation scheme, which is significantly faster than Gummel's scheme in cases where it converges slowly, thereby avoiding the drawbacks of a simultaneous solution method. This relaxation scheme has been implemented in the two-dimensional device simulator GALENE II.>

Recent trends in the integration of process-, device-, and circuit-modeling tools and the current rapid emergence of Unix-based computing environments of networked workstations and computer engines makes possible user-friendly, task-based CAD systems for technology optimization, characterization, and cell design. The authors discuss these trends and identify opportunities to use technology CAD tools in the development of competitive technologies and products. It is shown that the ability to provide design centering and extreme-case analysis related to process variables has been a key to aggressive design of robust IC products. This capability results from efforts in the early to mid-1980's to establish integrated modeling systems such as MECCA, the application of general-purpose optimization capabilities such as WATOPT and CENTER, and recent advances in open and powerful computing environments (principally Unix-based distributed resources).>

Most numerical MOS-simulators are based on Gummel's nonlinear relaxation method, for which severe convergence problems arise above threshold. A new hierarchical approach for the numerical simulation of MOS-transistors (MOST's) is presented, which overcomes these shortcomings resulting in an improvement of convergence speed of more than one order of magnitude.

A modular circuit is defined as a combination of a certain number of k-modules, which are embedded in a carrier network. The modules may represent subcircuits of varying complexity down to single devices. Such modular circuits lend themselves to a description by a system of modular equations. MEDUSA is a user-oriented simulator which utilizes system modularity during the simulation process itself, i.e., for solving the underlying equations. This approach enables the consistent numerical solution of both the basic equations of several bipolar devices and the network equations for a circuit environment. Hence, MEDUSA in its present state is a merged device-circuit simulator meeting simultaneously the requirements of device and circuit design.